3.1 Device Fabrication 3.1.1 TFT Fabrication
In order to make sure the Zn1−xZrxO TFTs have lower off current, we demonstrated the Zn1−xZrxO-based TFT with a conventional structure, to fabricating easily and efficiently. The device structure of Zn1−xZrxO based -TFTs as shown in Fig. 3.1 is the bottom-gate type and was fabricated by the following sequence of processes. The metal MoW was deposited on the glass substrate as a bottom gate electrode. Silicon nitride served as the gate insulator with a thickness of 3000 Å. The source and drain electrodes were made up of indium-tin oxide (ITO) and channel width and length were 500 and 50 μm, respectively. Finally, the Zn1−
xZrxO thin films were deposited by spin-coating with the processing parameters.
The device structure of Zn1−xZrxO -TFTs in bottom-gate type were fabricated by the Taiwan TFT LCD Association (TTLA). The Zn1−xZrxO film were fabricated by spin coater in the National Nano Device Laboratories (NDL).
3.1.2 Deposition of Active channel layer by spin-coating
Table 3.1 shows experimental flow chart of sol-gel precursor preparation. The Zn1
−xZrxO sol-gel precursors were synthesized by the mixing of znic acetate {Zn(CH3COO)2 · 2H2O} and zirconium isopropoxide {Zr[(CH3)2CHO]2}
dissolved in 2-methoxyethanol and monoethanolamine (MEA), and the solutions were stirring at 60°C for 30 min. The nominal x value for Zn1−xZrxO is 0.03.
Zn0.97Zr0.03O thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films were immediately baked at 300°C for
10 min on the Hot-plate. The rotation rate of the spin coater is 400 rpm, 15 seconds for step1 and 2000 rpm, 20 seconds for step 2.
3.1.3 Baking
After deposited by spin coating, the films were dried at 300°C for 10 min over a hot plate to evaporate the solvent and remove organic residuals. The procedures from coating to drying were only one times until the desired thickness of the sintered films was reached.
3.1.4 Patterning
There are many scientific or technical literatures which report HCl and HNO3
can etch ZnO films, but the etching rate of HCl and NHO3 solution is too fast for the Zn0.97Zr0.03O films. It will damage the Zn0.97Zr0.03O pattern and exhibit a lateral etching phenomenon. So, it mixed with the CH3COOH as buffer solution to reduce the etching rate. The optimal solution rate as H2O: CH3COOH: HCl/HNO3 : = 1 : 2 : 40. HNO3 for the Zn0.97Zr0.03O films is main etching solution. In this section, Zn0.97Zr0.03O films are patterned by photolithography and wet-etching with the solution mention above.
3.1.5 Annealing
The electrical characteristic of Zn0.97Zr0.03O-based TFTs are closely related to its crystal structure and oxygen vacancies (Vo), which can be controlled by doping or annealing conditions in oxygen atmosphere. In general, the intrinsic defects in ZnO films include oxygen vacancy (Vo), interstitial znic (Zni), etc. However, these defects can affect the electron concentration. The influence of oxygen vacancies (Vo) on the conductivity of the Zn0.97Zr0.03O has been confirmed in the annealing temperature. For Zn0.97Zr0.03O thin film, the change in the concentration of the oxygen vacancy (Vo) could lead to the change of the electron concentration and
hence make the bulk change from semiconductor to conductor. In this section, vacuum annealing furnace was used as annealing equipment and samples were used annealing temperature at 350°C for 1 hr under oxygen ambient 0.6 torr for TFTs.
3.1.6 Film Thickness
In general, the physical characteristics of polycrystalline semiconductors are easily modified by their crystallite sizes and boundary effects. The electrical properties are much more easily disturbed as long as the band structure altered inside the crystallites from the optical properties. The size of crystallites and the magnitude of the associated grain-boundary effects are dependent upon the preparation and treatment method, such as temperature in deposition or annealing, sputtering process, and deposition technique. In this section, the Zr0.03Zn0.97O films were prepared by spin-coating with 2 times and the thickness about 1100~1200 Å.
3.2 Instruments and measurement setup 3.2.1 Instruments
(1) Microscope、Probe station, as shown in Fig. 3.2
(2) Agilent 4284A、Agilent E5250A (Switch) and Agilent HP4156C
, as shown in Fig. 3.3
(3) Temperature controller, as shown in Fig. 3.4
(4) TTP-6 Probe Station, as shown in Fig. 3.5
(5) Software of measurement
ICS(Interactive Characterization Software)
Use the software to get :
VDS-IDS
VGS-IDS (Linear Region)
VGS-IDS (Saturation Region)
VGS-Gm
Note：VDS : Drain voltage IDS : Drain current
VGS : Gate voltage
IGS : Gate current
Gm : VGS - IDS max slope
3.1.2 Set up instruments for I-V
The current – voltage characteristic measurement of thin film transistor devices was performed by HP4156C semiconductor characterization system with source grounded and body floating.
The electrical test setup of HP4156C semiconductor characterization system, illustrated at Fig. 3.3, a probe station situated inside a dark box. The ground probe station is furnished with an electrically isolated, thermal chuck. The chuck is controlled by LakeShore 331 thermal controller, which can operate temperature from 77K to 400K. A semiconductor characterization system of Agilent HP4156C provides I-V measurement, bias for BTS. The HP4156C are connected to B2201A low leakage switch mainframe, and then link to dark box.
The current-voltage (I-V) characteristics measurements were gotten by using n-TFT and p-TFT structure with Agilent HP4156C semiconductor characterization system. Agilent HP4156C can measure the minimum leakage current: 1f (A).