This section describes the cell fabrication process including spin coating, lithography, wet etching, sputtering, annealing, rubbing, assembling. The detail process steps were listed below and as shown in Fig. 2-1.
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Fig. 2- 1 Fabrication steps
Glass cleaning
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I. Glass cleaning
For the transparent characteristic, glass has been widely used as the substrate for the display. In the fabrication, the glass of 0.55 mm thick is chosen and coated with ITO thin film already. The detailed sequence is as follow:
Step 1 : Place the glasses on the Teflon carrier, and put into a container with acetone as shown in Fig. 2-2. Ultrasonic vibrate for 20 minutes to remove the organic contamination on the glasses.
Step 2 : Rinse the glasses by DI water for 1 minute.
Step 3 : Rubbing the glasses with detergent by hands.
Step 4 : Rinse the glasses by DI water for 1 minute.
Step 5 : Place the glasses on the Teflon carrier, and put into a container with DI water as shown in Fig. 2-2. Ultrasonic vibrate for 40 minutes to remove the remained particle and detergent on the glass.
Step 6 : Use N2 purge to dry the glasses, and place glasses into a glass container with a cover.
Step 7 : Put the glass container into an oven with 110℃ for 30 minutes.
Fig. 2- 2 Schematic picture of step1 and step 5
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II. ITO pattering and insulator
The gate ITO pattering detailed sequence is as follow and also can refer to Fig. 2-4.
Step 1: Before the lithography process, glass substrate was cleaned by step I.
Step 2: Put the glasses on the metal holder and put into the HMDS oven to eliminate the surplus steam and improve the adhesion between organic photoresist and the ITO film.
Step 3: A positive photoresist was applied and coated on the ITO film.
Step 4: Soft bake for one and a half minutes, to eliminate most of the solvent of the photoresist and enhance the adhesion.
Step 5: Expose the glass with ultra-violet (UV) light source through shadow mask for 40 seconds. Consequently, the pattern on the mask was transformed to the positive photoresist after developing. The mask is shown in Fig. 2-3.
Step 6: Check the pattern by optical microscope (OM), to see if there is any broken line, and the hard bake for three minutes.
Step 7: Use wet etching technique and remove the photoresist, and the desired ITO pattern can be reserved.
Fig. 2- 3 The mask pattern of gate substrate and bottom lock 75um
12um
40um
30um
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Fig. 2- 4 Flow of fabricating gate ITO electrode (a) glass substrate with ITO film,
(b) spin-coating positive photoresist upon the glass substrate, (c) using lithography technique to obtain the latent image, (d) using leave-off technique to remove photoresist and reserve
the desired ITO pattern
ITO
Glass substrate
Photoresist
Photoresist ITO
ITO (Gate)
(a)
(b)
(c)
(d)
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The insulator and source/drain ITO pattering detailed is as follow and refer to Fig.
2-6.
Step 1: Use PECVD (Plasma-enhanced chemical vapor deposition) to produce 300nm thick SiO2 insulator.
Step 2: Put the glasses on the metal holder and put into the HMDS oven to eliminate the surplus steam and improve the adhesion between photoresist and ITO.
Step 3: A positive photoresist was applied and coated on the insulator.
Step 4: Soft bake for one and a half minutes, to eliminate most of the solvent of the photoresist and enhance the adhesion.
Step 5: Expose the glass with ultra-violet (UV) light source through shadow mask for 40 seconds. Consequently, the pattern on the mask was transformed to the positive photoresist after developing. The mask is shown in Fig. 2-5.
Step 6: Check the pattern by optical microscope (OM), to see if there is any broken line, and the hard bake for three minutes.
Step 7: Sputter ITO upon the patterned photoresist.
Step 8: remove the photoresist, and the desired ITO pattern can be reserved.
Step 9: RIE (Reactive-ion etching) process is used to remove the insulator where cover on the gate ITO soldered area. The pattern is shown in Fig. 2-7.
Fig. 2- 5 The mask pattern of source/drain substrate and top lock
72.5um
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Fig. 2- 6 Flow of fabricating insulator and source/drain ITO electrode (a) SiO2 insulator on gate substrate,
(b) spin-coating positive photoresist upon the glass substrate, (c) using lithography technique to obtain the latent image, (d) sputtering ITO,
(e) using leave-off technique to remove photoresist and reserve the desired ITO pattern
ITO SiO
2Photoresist
Photoresist SiO
2ITO
ITO (Source/Drain) SiO
2( Insulator)
(a)
(b)
(c)
(d)
(e)
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Fig. 2- 7 The pattern after RIE and the lock III. High-resistance layer and annealing
The high-resistance layer after sputtering a-IGZO can refer to Fig. 2-8. The high vacuum sputter system in NCTU with background pressure about 3×10-6 torr was placed in class 14K clean room. Vacuum system composes of rotary pump and cryo pump, which work for different pressure range. Power system consists of several DC and RF power modules with 6 sputtering guns and the purified gas sources of argon, nitrogen, and oxygen gas. The substrate planetary rotation system can bring uniformity by rotating the sample disk and holders.
Fig. 2- 8 High-resistance a-IGZO on the substrate
RIE
100um
100um
IGZO (Active layer) SiO2( Insulator)
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The a-IGZO active layer with 80nm in thick was deposited upon the substrate we made sputtering with an In2GaZnO5 target at room temperature. The deposition was done at DC power = 100W without any intentional substrate heating, working pressure =3mtorr and argon flow rate = 10sccm [28].
Finally, the device was annealed in nitrogen ambience at 350℃ for an hour by atmospheric anneal furnace to rearrange the a-IGZO lattice again. After annealing process, the electrical characteristics of the device are better than the device without annealing.
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IV. LC alignment layer and assembling
Step 1: Cleaning the patterned glass with step I.
Step 3: Coating the solvent to make the PI adhesion more efficiently.
Step 4: Coating the PI.
Step 5: Put the glasses into an oven with 220℃ for 60 minutes.
Step 6: Rubbing the glasses with parallel to the ITO pattern and make the rubbing direction mark.
Step 7: Paste two line spacers (30μm) on two sides of bottom glass and apply UV glue on the spacers.
Step 8: Make sure the top and bottom electrode overlap to each other. Then, put the bottom glass on the top glass and fixed with a tape.
Step 9: Press on both top and bottom glasses to make sure the cell gap identically.
Step 10: Fill in the LC after curing.
Step 11: Seal the edge with UV glue and curing.
The ultrasonic solder was soldered on the electrode to enhance the adhesive of the solder and smeared with AB glue to avoid the wires coming off. Finally, the High-resistance TFT Liquid Crystal Lens (HR-TFT LC lens) will be measured.
Fig. 2- 9 Prototype of HR-TFT LC lens 75um
14.5um
33 direction was controlled by the voltage and the HR-TFT LC lens was able to act as a GRIN lens and focused at a certain point. By placing CCD at the focal point of the HR-TFT LC lens, the intensity image and beam size of the HR-TFT LC lens could be measured.
Fig. 2- 10 Experimental setup II. Electrical characteristics
The device electrical properties and transfer characteristics for a-IGZO TFTs are measured by a semiconductor parameter analyzer (Keithley 4200) in the dark at room temperature. In the transfer characteristic (IGS-VDS), the VDS are conventionally swept from -10 to 30V at the step VGS (step = 0.5V) to measure the corresponding IDS.
In our experiment, the HR-TFT LC lens is measured by these two methods, and the results will be given in Chapter 4.
Beam