The MBNE algorithm integrates the aforementioned three algorithms. We first per-form clustering to reduce the problem size level by level and then enter the declus-tering stage. In the declusdeclus-tering stage, we perform floorplanning for the modules at
Figure 3.7 illustrates an execution of the MBNE algorithm. For explanation, we cluster three modules each time in Figure 3.7. Figure 3.7(a) lists seven modules to be packed, mi’s, 1≤i≤7. Figure 3.7(b)-(d) illustrates the execution of the clus-tering algorithm. Figure 3.7(b) shows the resulting configuration after clusclus-tering m5, m6, and m7 into a new cluster module m8 (i.e., the clustering scheme of m8 is {{m5,m6},m7}). Similarly, we cluster m1,m2, and m4 into m9 by using the cluster-ing scheme {{m2, m4}, m1}. Finally, we cluster m3,m8, and m9 into m10 by using the clustering scheme {{m3, m8}, m9}. The clustering stage is done, and the declus-tering stage begins, in which ²-neighborhood and λ-exchange method are applied to refine the coarse floorplan. In Figure 3.7(e), we first decluster m10into m3, m8, and m9 (i.e., expand the node n10 into the B*-subtree illustrated in Figure 3.7(e)). We then move m8 to the top of m9 (perform Op2 for m8) during ²-neighborhood and λ-exchange refinement (see Figure 3.7(f)). As shown in Figure 3.7(g), we further decluster m9 into m1, m2, and m4, and then rotate m2 and move m3 on top of m2 (perform Op1 on m2 and Op2 on m3), resulting in the configuration shown in Figure 3.7(h). Finally, we decluster m8 shown in Figure 3.7(i) to m5, m6, and m7, and move m4 to the right of m3 (perform Op2 for m4), which results in placement with good quality shown in Figure 3.7(j).
Figure 3.7: An example of MBNE algorithm.[10]
Chapter 4
Experimental Results
We implement the MBNE algorithm in C++ programming language. The platform is Intel Pentium 4 2.4GHz CPU with 1.5GB memory. We make the comparisons with the MB*-tree algorithm on benchmarks including industry[10], MCNC[19]
and GSRC[20] suites for area, wirelength and simultaneous area and wirelength optimizations.
4.1 Industry with MB*-tree (Area, Wirelength, Area/Wirelength)
The circuit industry is a 0.18µm, 1GHz industrial design with 189 modules, 20 million gates and 9,777 center-to-center interconnections. It is a large chip design and consists of three modules with aspect ratios greater than 19 and as large as 36.
In each entry of the table, we list the best/average values obtained in ten runs of MBNE and MB*-tree.
Table 4.1 shows the results of MBNE compared with MB*-tree. For area op-timization, MBNE can obtain a dead space of only 1.99% while MB*-tree results in a dead space of 2.32%. For wirelength optimization, MBNE can obtain a total wirelength of only 53723 mm while MB*-tree requires a total wirelength of 55971 mm. For simultaneous area and wirelength optimization, MBNE can obtain a dead
space of 9.95% and wirelength of 63583 mm while MB*-tree requires 14.45% and 67179 mm.
Area optimization Wirelength optimization
Area Dead space Time Wirelength Time
Package
(mm2) (%) (min) (mm) (min)
MBNE 671.32/674.57 1.99/2.45 4.00/3.47 53723/58585 150.28/150.18 MB*-tree 673.60/679.41 2.32/3.15 3.95/3.84 55971/59759 180.45/184.54
Simultaneous area and wirelength optimization Table 4.1: Comparisons for area optimization alone, wirelength optimization alone, and simultaneous area and wirelength optimization between MBNE and MB*-tree based on the circuit industry.
4.2 MCNC - ami49 1-200 with MB*-tree (Area)
The ami49 is the largest MCNC benchmark circuit, and we created seven synthetic circuits, named ami49 x, by duplicating the modules of ami49 by x times to test the capability of our algorithm. The largest circuit ami49 200 contains 9800 mod-ules. Table 4.2 shows the result of MBNE compared with MB*-tree. The MBNE obtains 0.3%-1.34% improvement in dead space compared with MB*-tree for the seven ami49 x circuits.
4.3 GSRC - n100-300 with MB*-tree (Area, Wire-length)
The n100, n200, and n300 are the three GSRC benchmark circuit. We used them to compare the MBNE with MB*-tree for area and wirelength optimizations. Table 4.3 shows the number of modules, number of nets, and total area of the GSRC
# Total MB*-tree MBNE Improvement modules area Area Dead space Time Area Dead space Time in dead space Circuit
(mm2) (mm2) (%) (min) (mm2) (%) (min) (%)
ami49 49 35.445 36.46 2.79 1.19 36.22 2.14 1.00 0.65
ami49 4 196 141.780 146.86 3.46 6.29 144.86 2.12 5.00 1.34
ami49 20 980 708.908 732.19 3.18 10.21 727.81 2.60 10.08 0.58
ami49 60 2940 2126.724 2211.75 3.84 16.73 2195.76 3.14 15.17 0.70
ami49 100 4900 3544.540 3704.65 4.32 20.47 3681.56 3.72 20.18 0.60
ami49 150 7350 5316.750 5590.95 4.90 26.77 5560.33 4.38 25.58 0.52
ami49 200 9800 7089.808 7478.55 5.21 31.65 7454.86 4.91 30.13 0.30
Table 4.2: Comparisons for area, dead space, and runtime between MBNE and MB*-tree with the MCNC benchmark.
Table 4.4 shows the results of MBNE compared with MB*-tree. For area op-timization, MBNE can obtain dead space of only 1.64%, 2.09% and 2.08% while MB*-tree results in dead space of 2.62%, 2.39% and 2.20%. For wirelength opti-mization, MBNE can obtain total wirelength of only 110.982 mm, 241.696 mm and 388.162 mm while MB*-tree requires total wirelength of 111.819 mm, 244.233 mm and 391.651 mm.
4.4 Efficiency with MB*-tree
We choose four circuits from the industry, MCNC, and GSRC benchmark to com-pare for efficiency between MBNE and MB*-tree algorithm. We set the runtime of MBNE equal to 70% runtime of MB*-tree algorithm for four circuits. Table 4.5 shows the results of area, dead space and runtime of MBNE and MB*-tree. MBNE obtains dead space of 2.34%, 2.11%, 2.89% and 2.32% while MB*-tree requires dead space of 2.32%, 2.62%, 3.18% and 3.84% in these four circuits.
Circuit # of modules # of nets Total area (0.001mm2)
n100 100 885 179.50
n200 200 1585 175.70
n300 300 1893 273.17
Table 4.3: The number of modules, number of nets, and total area of the GSRC benchmark.
Area optimization Wirelength optimization Area Dead space Time Wirelength Time
n100 (0.001mm2) (%) (min) (mm) (min)
MBNE 182.490 1.64 5.00 110.982 10.03
MB*-tree 184.338 2.62 5.17 111.819 10.89
Area optimization Wirelength optimization Area Dead space Time Wirelength Time
n200 (0.001mm2) (%) (min) (mm) (min)
MBNE 179.452 2.09 7.00 241.696 15.37
MB*-tree 180.000 2.39 7.78 244.233 15.94
Area optimization Wirelength optimization Area Dead space Time Wirelength Time
n300 (0.001mm2) (%) (min) (mm) (min)
MBNE 278.964 2.08 10.01 388.162 20.40
MB*-tree 279.310 2.20 10.17 391.651 21.45
Table 4.4: Comparisons for area and wirelength optimization between MBNE and MB*-tree with the GSRC benchmark.
# Total MB*-tree MBNE Improvement
modules area Area Dead space Time Area Dead space Time in time
Circuit
(0.001mm2) (0.001mm2) (%) (min) (0.001mm2) (%) (min) (%)
industry 189 657,984 673,600 2.32 3.95 673,731 2.34 2.77 29.9
n100 100 179.500 184.338 2.62 5.17 183.365 2.11 3.61 30.2
ami49 20 980 708,908 732,190 3.18 10.21 729,982 2.89 7.57 25.9
ami49 60 2940 2,126,724 2,211,750 3.84 16.73 2,199,793 3.32 11.73 29.9
Table 4.5: Comparisons for efficiency between MBNE and MB*-tree with four bench-mark.
Chapter 5
Conclusion and Future Works
In this thesis, we have shown the approaches on the multilevel hierarchical floor-plan/placement for large-scale circuits. With the MBNE algorithm, we can choose to optimize area only, wirelength only, or simultaneous area and wirelength with any ra-tio of the placement. Our MBNE algorithm combines the B*-tree representara-tion and multilevel framework of MB*-tree, and the improved format of ²-neighborhood and λ-exchange refinement method. Experimental results have shown that the MBNE algorithm has better performance compared with the MB*-tree, state of the art floorplanner, in several benchmarks.
For future improvement of our placement method, developing the locally per-turbation of later declutering level may solve the scalability of increased number of modules. Or we can adopt the ²-neighborhood and λ-exchange refinement method to another framework of algorithm, this may improve its performance.
Acknowledgement
We thank Mr. Hsun-Cheng Lee and Prof. Yao-Wen Chang for their MB*-tree platform and industry benchmark.
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作者簡歷
王冠中，民國六十七年六月出生於台北市。民國九十年六月畢業於國 立交通大學電子工程學系，並於同年八月入伍服役。民國九十二年九 月進入國立交通大學電子研究所就讀，從事 VLSI 實體設計方面相關 研究。民國九十四年六月取得碩士學位，碩士論文題目為『多層架構 的鄰近單元交換方法之大型電路佈局』。