In our proposed architecture, the 4 x 4 block mode decision part and the macro block mode decision pa rt are designed separately. Actually we can find that each direction values of a macro block are just accumulations of every 4 x 4 block in mode 0, mode 1, mode 3 and mode 4. That means there still a lot of duplicate computations between 4 x 4 block mode d ecision and macro block mode decision. Hence we should explore a method to combine both circuits together to raise hardware utilization and reduce area size.
For 4 x 4 intra prediction mode decision , DC mode (mode 2) is the most mode which be chosen after rate-distortion optimization because the flat plane such as human face, clothes and sky always appear in the natural video. According to the experiments, we can explore another architecture to decide the best choose is mode 2 or not with our design. If mode 2 is chosen, the other calculations for proper direction detection can be avoided. And we can reduce more rate -distortion computations and accelerate the intra prediction mode decision if DC mode is always chosen.
Chapter 5
Conclusion
In this thesis, the low cost and high performance architecture for fast intra mode prediction is explored and implemented. The main contributions come form three part;
they are 4 x 4 block gradient vector calculator, direction decision and the 4 x 4 blo ck mode decision respectively.
For block gradient vector calculation, butterfly architecture of vector calculator and the block type memory access scheme are proposed. Both architectures generate the value of Gx and Gy of each visual pixel cycle by cycle and hence we don’t need other spaces for saving the incomplete values during the course. By using this scheme, we reduce not only the hardware spend but also the blocking time of the first processing 4 x 4 block.
For direction decision, we observe that th e sign bit contains the information of direction. So by using the sign bits and values of Gx and Gy immediately, it only needs one processing cycle to find the proper direction of each 4 x 4 block. And the total processing stages of the 4 x 4 processing co re then become two stages, one stage less than Li’s design and lots hardware reducing than Li’s too.
For mode decision of 4 x 4 blocks, we design a five-values-sorting circuit with extra hardware for mode checking to replace eight-values-sorting method. This hardware pick up the top three values at every cycle and the exact result of each 4 x 4 block would be gave at the interval of nine cycles. That means we don’t need another
time for processing between blocks and hence the architecture is not only smal ler but also faster than Li’s.
As we can see in the results, the architecture we design for fast intra prediction mode decision keeps the same video quality as Li’s but implemented with almost half less hardware. On the other hand, the maximum operating frequency and the processing cycle for one macro block of our hardware are also higher and shorter than Li’s, and these advantages make our proposed design more suitable when we take high resolution into consideration of the real -time applications.
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