Future Research Directions

The presented GDA design approach involves cyclic convolution, its partitioning scheme, and hardware efficient GDA implementation. Since the linear convolution and correlation own similar characteristics to cyclic convolution, if any DSP algorithm can be expressed as cyclic convolution, we can apply the proposed GDA design approach to achieve efficient hardware cost for applications.

On the power consumption point of view, with the approach of address grouping in the proposed GDA design, we will further explore how to decide the set of seed partial products for groups in the memory module of GDA design to have optimal transition activity on the bit-line of memory and achieve lower power consumption. However, since the optimal arrangement of these seed partial products depends on the characteristic of image sequences as well as the distribution of input

data, there should exist an optimal arrangement of seed partial products for each kind of image sequences.

For the application of prime-length DCT, since the prime length cyclic convolution DCT algorithm has less overhead in the pre- and post- processing, the GDA-based variable-length DCT design should be an alternative hardware-efficient DA solution for the shape adaptive discrete cosine transform (SA-DCT) in MPEG-4 codec application. However, since there exist more overhead in non-prime length cyclic convolution DCT, this part of realization in SA-DCT must be combined with the existing DA design or the other efficient design.

Based on the derivation of DSST’s in cyclic convolution, a unified GDA-based design of DSST’s should be a considerable approach for the hybrid system with the requirements of multimedia and communication such as the portable devices. With a commonly used memory module in the GDA design, we can preload the corresponding partial products, and configure the design with different data flow for computations of the involved DSST’s. Actually, with the acceptable overhead in cyclic convolution algorithm, a unified DFT/IDFT should be the possible design for communication applications. However, for a long time, the approaches of general purpose design and dedicated design have been the traded-off between flexibility and hardware cost.

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VITA

Hun-Chen Chen was born in Taiwan in 1961. He received the B.S. and M.S degrees, all in electronics engineering, from National Taiwan Technology University, and National Chiao-Tung University, Taiwan, in 1990 and 1998, respectively. He is currently pursuing the Ph.D. degree in low-cost bit-level DSP VLSI design and its applications to multimedia and communication systems. His research interests include VLSI digital signal processing and computer architecture.