Chapter 5 Conclusions
5.2 Future Work
The thesis has had superiority in the biomedical signals recording system
according to the result of the AFEIC post-layout simulation. However, the AFEIC is still worth improving further in the future. For example, reduce the phase delay in the SCLPF, consume lower power, use battery to supply the power of AFEIC, integrate with digital circuit, ADC and embedded system, has fewer noise, etc.Reference
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Appendix A. DRC Verification
Whole Chip DRC
圖I 全系統晶片之 DRC 驗證
其中DRC ERROR 為I/O PAD內部錯誤，錯誤訊息皆在PAD，為可忽略的錯，如 圖II所示。
圖II 可允許DRC錯誤說明
B. LVS Verification
圖III 全系統晶片之 LVS 驗證無誤
C. Tapeout Review Form
Tapeout review form 的用意在提醒設計者在設計、模擬、佈局、佈局驗證及 tapeout 時具備 設計理念及了解應注意事項,希望能藉此提昇晶片設計的成功率及達到完整的學習效果。因此,請
3 Power Line 佈局考量
6-4 下線者是否有使用該製程設備之經驗?______
7-3 模擬軟體 (可不只一種)? _____________________
7-4 系統整合chip 裡之各個 block 是否曾下過線且量測符合預期規格 (chip 為系統整合者
7-6 DRC 驗證過程中, 部分錯誤若為特殊考量, 請說明____________________________
________________________________________________________________________
使用的 metal layers 的層數:
佈局中 ARM926EJ /ARM7TDMI Macro 的 cell name:
這個晶片是否為修訂版本(revision,也就是之前曾下線過相同晶片)？
若是修訂版本，前一次下線的晶片編號:
修訂版本的原因是？(例如修正 bug) 10 其他考量
10-1 是否考量測試時的輸出量測點? 是
10-2 是否考量電路之可修改性(如用 laser cut 設備) 是
設計者簽名:___戴毓廷______ 指導教授簽名:___林進燈____