Switched-Capacitor Low-Pass Filter (SCLPF)

Typical passive filter and active filter are very bulky and not suitable for IC fabrication. The biomedical signals distribute over very low bandwidth such as EEG signals distributed from DC to 150Hz. We regarded the EEG bandwidth as the filter bandwidth, must filter the high frequency noise above 150Hz. If adopt the general active filter to set up 150Hz in 3dB frequency, certainly the filter will use the large resistor and capacitor to produce low poles. It is hard to realize the large resistor and capacitor in the CMOS fabrication because they occupy bulky area and they are also low accuracy and sensitive to temperature. Therefore, AFEIC used the switched-capacitor low-pass filter to realize a low-pass filter. It used some switches and capacitors to approximate a large resistor. They replace bulky resistors in traditional filter, so SCLPF can be integrated the system into a chip. First, set up switch frequency that is sampling frequency. Second, set up the sampling capacitor value. The frequency of EEG signals ranges from DC to 150Hz, so the lowest sampling frequency is 300Hz. However, other biomedical signals opposite to EEG should blend into the input-end and they can regard as noise. Most biomedical signals are within 1kHz so the sampling frequency is set up in 5kHz properly.

The switched-capacitor filter mentioned in documents can be divided into the following several structures: switched-capacitor ladder filter, switched-capacitor differentiator biquad filter, and switched-capacitor integrator biquad filter. AFEIC used the switched-capacitor integrator biquad second order filter. This structure can be divided into two kinds of high-Q and low-Q filter, and that is suitable for application of high frequency and low frequency separately. Due to the biomedical signals are all

switched-sharing to realize the filter. Switched-sharing can not only reduce the layout area but also save the dynamic power consumption. The architecture of the SCLPF is shown as Fig. 3-9 and the operation amplifier is shown as Fig. 3-10.

P₁

Fig. 3-9 The architecture of the SCLPF.

VDD

Fig. 3-10 An operation amplifier of the SCLPF.

We adjusted the clock in the SCLPF as Fig. 3-9 opposite to the first generation AFEIC. The reason is when the transistor state changed from on (1) to off (0), charge injection occurs. Charge injection [26][40] occurs by channel charge when MOS switches turn off. From Fig. 3-11, we can see the channel charge flow out from the channel region of the transistor to the drain and source junctions. High frequency switch produces a lot of digital noise by charge injection and affects the performance of the AFEIC.

Fig. 3-11 A concept of charge injection [40].

To avoid the above-mentioned, we should select a proper clock frequency in the Fig. 3-9. The first generation AFEIC has only two clock and this generation AFEIC utilizes four clock to switch [41] in this AFEIC design in order to reduce the digital noise of charge injection. Fig. 3-12 analyzes the influence of utilizing switch clock to reduce charge injection. Assume the phase of M1 and M2 are the same (P1=P1a) and the phase of M3 and M4 are the same (P2=P2a), and analyze the charge injection of each transistor.

Fig. 3-12 Analysis of charge injection.

(1) M1: When M1 state is from on to off, charge in the channel will flow to the capacitor C1. Different charge will flow to the capacitor C1 by different Vin.

This is a distorted source.

(2) M2: When M2 state is from on to off, charge in the channel will flow to the GND and Vin. Assume Vin is an ideal voltage source and the impendence of M1 is very small, so it has no influence to the circuit.

(3) M3: When M3 state is from on to off, charge in the channel will flow to the capacitor C1 and GND. It will affect the sampling voltage of C1, but it is a DC offset voltage that can be predicted. Therefore, it has few influences to the circuit.

(4) M4: When M4 state is from on to off, charge in the channel will flow to the capacitors C1 and C2. However, two ends are both DC offset voltage, so it has few effects to the circuit.

We adjusted the clock by the analysis drawbacks of the above. Let P1a turn off little earlier than P1, and P2a turn off little earlier than P2. Thus, right-end of the capacitor C1 becomes floating, and the charge in the channel of M1 and M3 can not move forward to C1. Consequently, it can not become a loop, so can reduce the effect

of charge injection.

From the analysis of the above, mutual matching of four clocks can effectively reduce the influences of charge injection. Therefore, the non-overlapping clock generator in a SCLPF is shown as Fig. 3-13. In order to assure the output of the clock generator correctly, we adjusted appropriate transistor size in the output inverter.

CLK

P2a P1a

P2 P1

Fig. 3-13 Non-overlapping clock generator.

The pre-layout simulation of the operation amplifier in the SCLPF is shown as Fig. 3-14. The differential gain of the OP is about 80dB and the phase margin is about 75 degrees.

Fig. 3-14 The pre-layout frequency response simulation of the OP in the SCLPF.

Gain=80dB PM=75degree

Additionally, the non-overlapping clock generator provided four non-overlapping phases to switch controlling switch, and the clock transient response simulation is shown as Fig. 3-15. The top signal is input clock among the figure, and output signals that are produced by the clock generator are P1, P1a, P2, and P2a in order. The pre-layout simulation of the SCLPF is shown as Fig. 3-16, Fig. 3-17, and Fig. 3-18.

The amplitude of input testing signal is 15mV (Take the largest EEG amplitude 100uV as an example, EEG signals via the CBIA and its output amplitude is about 14.125mV, so decide the testing signal is 15mV.) to test SCLPF with different frequency. The different frequency distributes over 10Hz (pass band), 150Hz (3dB band), and 1kHz (stop band) separately. The SCLPF really has the function of low pass filter from the input/output signals transient response simulation.

Fig. 3-15 The pre-layout transient response simulation of the clock generator.

Fig. 3-16 The pre-layout transient response simulation of SCLPF (pass band).

Fig. 3-17 The pre-layout transient response simulation of SCLPF (3dB band).

Fig. 3-18 The pre-layout transient response simulation of SCLPF (stop band).