Future Work

There are several improvements and extensions can be considered in the future:

• Combination of IQ and IDCT

Since the computation of inverse quantization is followed by IDCT, we can simply combine these computations to reduce the number of memory load/store.

• Data structure refinement

For the implementation on DSPs, the design of data structure is very important, which affects the performance highly. If we can design the more efficient data structure, the memory accesses can be significantly reduced, and the performance also can be improved.

• Dual-core implementation

Since the internal memory of PACDSP is 64 KB only and the access to external memory consumes much execution time, the amount of bitstream that is written to the memory is limited. Therefore, the number and the size of decoding frames are also constrained. However, the internal memory of PACDSP can be accessed by the ARM core on the PSDK platform, then we can manage the memory through ARM core, and the usable memory size is enlarged.

In addition, some functions like the VLD. Because it has many branch instructions in its decoding procedure, which degrades the performance of implementation on PACDSP. In other words, using PACDSP to implement the VLD has no advantage.

We can redesign the dual-core implementation, and use the suitable core module to implement each functions.

• Implement on PACDSP v3.0

In this thesis, we consider the implementation of MPEG-4 video decoder on PACDSP v2.0. However, the latest version of PACDSP is version 3.0 which support some new and useful instructions. We can further implement the decoder on PACDSP v3.0, and use the new instructions to improve the performance.

• Add other MPEG-4 tools

In our implementation, the tool of error-resilience in MPEG-4 simple profile is left. However, for the bitstream transmitted through a real channel, this tool is very important. We need to consider the implementation of error-resilience in the future. Moreover, we also can implement other advanced profiles of MPEG-4 video decoder for more decoding tools to extend the capability of PACDSP.

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自傳

許介遠，男，民國七十二年二月十八日出生於台灣省高雄市。高中 就讀於高雄中學。大學就讀國立交通大學電信工程學系，於民國九十

四年六月畢業。並在同年九月進入交通大學電子工程研究所碩士班，

於民國九十六年六月取得碩士學位，論文題目為:『MPEG-4 物件視訊

解碼器在 PACDSP 平台上之軟體實現』。研究範圍與興趣為：軟、硬體

和 DSP 平台上之系統整合與開發，主要應用範圍在多媒體訊號處理與

壓縮方面。