Chapter 2 Literature Review
5.1 Introduction
5.2.7 Gate formation
The gate slot was defined by AZ6310 photoresist, and the wafers were then dipped in the 20% HCl solution for 15 seconds to remove the native oxide fallowed by depositing Ti/Pt/Au by e-gun evaporation system. Finally, the wafer was immersed into ACE to lift-off the undesired metal. As the result, the gate length of the InAlAs/In0.7Ga0.3As MHEMTs in this chapter is 0.8μm.
5.3 Results and Discussion
Electrical characteristics of the 0.8μm InAlAs/In0.7Ga0.3As MOS-MHEMT and conventional MHEMT are plotted and analyzed. Fig.
5-3 demonstrates the diagram of drain current (ID) versus the drain voltage (VD), which indicates that the saturation current of the MOS-MHEMT is reduced referring to the conventional MHEMT at the
53
same gate-to-source voltage (VGS). The decline of the ID reveals the reduction of carrier concentration within the channel affected by the oxide layer, attributing to the larger barrier height between the gate metal and Schottky layer. As the result, the electrical field in the channel between gate and drain is decreased, leading to the capability for biasing at higher VD. Extrinsic transconductance (Gm) versus gate-to-source voltage (VGS) curves are displayed in Fig.5-4. Due to the influence mentioned above, the Gm peak of the MOS-MHEMT is compressed from 215 mS/mm to 170 mS/mm.
The breakdown voltage diagram is illustrated in Fig. 5-5. At the beginning, the leakage current increases dramatically, where might caused by the defects of the MHEMT structure. However, the MOS-MHEMT displays smaller slope of the curve which implies the oxide layer could effectively decrease the leakage current. In addition, after introducing Al2O3 as gate insulator, the leakage current is reduced about one order, where is observed in the Fig. 5-6.
Table 5-2 summarizes the logic parameters of the InAlAs/In0.7Ga0.3As MOS-MHEMT and conventional MHEMT. All the parameters are defined as the chapter 3 exhibits and measured at a VDS of 0.5volts. In comparison with the conventional MHEMT, MOS-MHEMT shows almost the same logic performance. The slightly larger subthreshold slope (SS) is due to the increase of the gate-to-channel distance which attributes to the insertion of the Al2O3 layer between the metal and Schottky layer. In addition, the worse drain induced barrier lowering (DIBL) value is because of the reduction of carrier concentration within the channel, contributing to the reduction of the
electric field. Therefore, MOS-HEMT requires larger bias voltage to function device, where manifests the decline of the DIBL parameter.
Overall, the MOS-MHEMT device not only displays fantastic insulating property but presents almost the same logic performance parameters in Gm, SS and DIBL without dramatically decreasing. Those results indicate the possibility of MOS-HEMT for logic application.
5.4 Conclusions
The 0.8μm InAlAs/In0.7Ga0.3As MOS-MHEMT and conventional HEMT were fabricated, and the parameters for low-power digital applications were calculated for comparison. MOS-MHEMT exhibits better insulating property, meanwhile, the digital parameters are almost the same. That result leads to the possibility of InAlAs/In0.7Ga0.3As MOS-MHEMT for digital utilization. Further gate length scaling down is necessary to improve the device performance.
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Table 5-1 Comparison of relevant properties for high-K candidates
Table 5-2 Logic parameters of the 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT and conventional HEMT
Fig. 5-1 Structure of 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT
Fig. 5-2 Process flow of 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT
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Fig. 5-3 Drain current (ID) versus the drain voltage (VD) curves of the 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT and conventional HEMT
Fig. 5-4 Extrinsic transconductance (Gm) versus gate-to-source voltage (VGS) curves of the 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT
InAlAs/In0.7Ga0.3As mHEMT with oxide
InAlAs/In0.7Ga0.3As mHEMT without oxide
with oxide Lg=0.8m
Fig. 5-5 Gate-to-drain breakdown voltage (BVDG) of the 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT and conventional HEMT
Fig. 5-6 Gate leakage current density performance of the 0.8μm InAlAs/In0.7Ga0.3As MOS- MHEMT and conventional
0 5 10 15 20
0.0 0.2 0.4 0.6 0.8 1.0
InGaAs MOS-mHEMT Lg=0.8m
without oxide with oxide Leackage current, I G(mA/mm)
VD(V)
-0.6 -0.4 -0.2 0.0
1E-4 1E-3 0.01 0.1 1
InAlAs/In0.7Ga0.3As mHEMT without oxide
with oxide
VDS=0V & 0.5V, Lg=0.8m Leackage current, I G(mA/mm)
VGS(V)
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Chapter 6
Employing Air-bridge Structure on InAlAs/InAs MOS-HEMTs for
Digital Applications
6.1 Introduction
For further digital performances improvement of the InAlAs/In0.7Ga0.3As MHEMT, endowed with high electron mobility (33,000 cm2V−1s−1) and high saturation drift velocities (8×107cm/sec), InAs is expected to be the solution to the channel material to improve the device performance for the next generation utilization.
However, conventional InAlAs/InAs MHEMTs drastically suffer from low breakdown voltages due to the enhanced impact ionization effects that occur in the narrow-bandgap InAs channel[2]. Further insulating layer is necessary to be employed to reduce the effects, as the former chapter shows. After the ALD Al2O3 is introduced, the carrier concentration within the channel is reduced affected by the oxide layer, attributing to the larger barrier height between the gate metal and Schottky layer.
Another issue is worth noticing that devices with different gate width are needed for different level usage. Fan-out is a measure of the ability of a logic gate output, implemented electronically, to drive a number of inputs of other logic gates of the same type. Therefore, employing the air-bridge structure on InAs MOS-HEMTs could fabricate devices with
different amount of driving current.
In this study, we focus on the characteristics of the 0.8μm InAlAs/InAs/InP MOS-HEMTs with air-bridge structure. Devices with various gate widths were fabricated and the electrical characteristics were also investigated to identify the similarity of the performance. Besides, including subthreshold slope (S), drain-induced barrier lowering (DIBL) and ION/IOFF ratio, above figures of merit (FOM) for logic application will also be exhibited to realize the logic potential of MOS-HEMTs.
6.2 Device Fabrication
The epitaxial layers of the InAlAs/InAs HEMTs were grown by molecular beam epitaxy (MBE) on InP substrate. The schematic cross-sectional view of our δ-doped InAlAs/InAs MOS-HEMT structure is shown in Fig. 6-1.
Fig. 6-1 shows the illustration of δ-doped InAlAs/InAs HEMT which consists of, from bottom to top, InAlAs buffer layer, In0.70Ga0.30As/InAs/In0.70Ga0.30As composite channel, InAlAs spacer layer, δ-doped carrier supply layer with Si doping concentration of 5.0×1012/cm2, InAlAs Schottky layer, InP etching stop layer, and n-InGaAs cap layer with Si doping concentration of 2.0×1019/cm3. It is worth noticing that the high etching selectivity between InP and InAlAs is of importance for device fabrication, attributing to the 1st recess is done before Ohmic formation due to the post-depositing annealing temperature of ALD
61
Al2O3 is higher than the rapid thermal annealing temperature of the Ohmic metal.
The detailed manufacturing process on the InAlAs/InAs MOS-HEMT device is described at the following sections. The flow chart of the process for device fabrication is illustrated in Fig. 6-2.
6.2.1 Wafer cleaning
The purpose of wafer cleaning is to remove undesirable impurities and particles on the surface. The wafers were immersed in Acetone (ACE) and isopropyl alcohol (IPA) each for five minutes, and blown dry by nitrogen gas.
6.2.2 Mesa isolation
The active region of devices is defined by S1818 photoresist, and other potions were wet etched to the buffer layer. The mesa isolation was carried out by H3PO4:H2O2:H2O (5:1:40) solution to etch the InGaAs cap layer and the InAlAs Schottky layer. HCl:H2O (1:1) solution to etch the InP etching stop layer. Then, the etching depth will reach about 4000Å by utilizing H3PO4:H2O2:H2O solution again. The etching depth is measured by α-step measurement.
6.2.3 1
strecess
The gate recess slot was defined by S1818 photoresist to form the pattern. Succinic acid (SA) based solution (SA:H2O2:H2O) was used to etch the cap layer and part of the InAlAs shottky layer.
6.2.4 Surface treatment
Here, we choose (NH4)SX as our surface treatment solution. The HCl:H2O (1:4) solution was applied for removing the native oxide, followed by dipping the wafer in (NH4)SX for 30 minutes at 60℃. The depth of the passivating thin film can be determined by the immersing time and reacting temperature.
6.2.5 Atomic layer deposition (ALD) Al
2O
3The process temperature of ALD Al2O3 is 300℃, and the uniform Al2O3 layer is deposited for the depth of 12μm, followed by the post-deposition annealing (PDA) at 500℃.
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The ohmic contact region is defined by AZ5214E photoresist with undercut profile. The wafers are dipped in HF: H2O (1:10) for 1 minute to remove the Al2O3, and 20% HCl solution for 15 seconds to remove the native oxide. Ohmic metal was then deposited on the substrates by using an electron-beam evaporator at a pressure of ~1x10-6 Torr. After ACE lift-off procedure, the wafer was thermally alloyed at 240℃ for 30 seconds by using rapid thermal anneal (RTA) system. After all, the contact resistance is observed via measuring the transmission line method (TLM), and the specific contact resistivity is 1.3945×10-7 Ω cm2.
6.2.7 Gate formation
The gate slot was defined by AZ6310 photoresist, and the wafers were then dipped in the 20% HCl solution for 15 seconds to remove the native oxide fallowed by depositing Ti/Pt/Au by e-gun evaporation system. Finally, the wafer was immersed into ACE to lift-off the undesired metal. As the result, the gate length of the InAlAs/In0.7Ga0.3As MHEMTs in this chapter is 0.8μm.
6.2.8 Device passivation
In order to protect the devices from environmental contamination and mechanical damages, the silicon nitride film (SiNX) was formed by PECVD. The wafer was first dipped in the solution of NH4OH:H2O=1:50 for 10 seconds to clean the surface and decrease the surface dangling bonds. The silicon nitride film was grown at 250℃. RF power was 35W, and the precursors were SiH4/Ar, NH3 and N2 . The film thickness was about 1000Å and its refractive index was about 2.0, which were measured by ellipsometer.
After the passivation process, the contact via was defined for interconnections. Then the silicon nitride film was etched by reactive ion etching (RIE) system. The reactive plasmas are CF4 and O2, the RF power is 80W, and the pressure is 60 mtorr.
6.2.9 Air-bridge plating
First, a layer of photo-resist was spun and patterned to open areas over metal pads. Then, a thin coating of Ti/Au/Ti was applied to the entire wafer, where Titanium is deposited to improve the adhesion. The thin metal layer can conduct the plating current to the whole wafer. Next, a second coating of photo-resist was applied and patterned. Then the wafer was electroplated with gold for 2μm thickness. After plating, the top resist layer, thin Ti/Au/Ti metal, and lower resist layer were removed individually, leaving only the plated air-bridge.
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6.3 Results and Discussion
Electrical characteristics of the 0.8μm InAlAs/InAs MOS-HEMT with various gate widths are plotted and analyzed. Fig. 6-3 demonstrates extrinsic transconductance (Gm) versus gate-to- source voltage (VGS) curves. The peak Gm of the devices slightly decreases as the gate width increases. Meanwhile, the driving current increases, which is shown in Fig.6-4. Moreover, the threshold voltage of each device doesn’t change a lot with the variation of the gate widths.
The breakdown voltage diagram is illustrated in Fig. 6-5, which displays high gate-to-drain breakdown voltage (BVGD) is achieved. All the BVGD of the InAlAs/InAs MOS-HEMT with various gate widths are around 17volts. In addition, the leakage current are reduced to less than 1
×10-7 A/device in the Fig. 6-6. Those diagrams imply the good insulating property of InAlAs/InAs MOS-HEMT employing air-bridge structure.
Table 6-1 summarizes the logic parameters of the InAlAs/InAs MOS-MHEMT. All the parameters are defined as the chapter 3 exhibits and measured at a VDS of 0.5 volt. All the devices with different gate widths perform almost the same logic performance, indicating that the possibility of InAlAs/InAs MOS-HEMT with different gate widths for logic applications of various fan-out level.
6.4 Conclusions
The 0.8μm InAlAs/InAs MOS-HEMTs with different gate widths were fabricated and the good insulating property was demonstrated.
Meanwhile, the digital parameters and threshold voltage don’t vary with the various gate widths, leading to the possibility of InAlAs/In0.7Ga0.3As MOS-MHEMT for digital utilization of different fan-out level. Further gate length scaling down is necessary to improve the device performance.
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Table 6-1 Logic parameters of the 0.8μm InAlAs/InAs MOS-HEMT with various gate widths
Fig. 6-1 Structure of 0.8μm InAlAs/InAs MOS- HEMT
Fig. 6-2 Process flow of 0.8μm InAlAs/InAs MOS-HEMT
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Fig. 6-3 Extrinsic transconductance (Gm) versus gate-to-source voltage (VGS) curves of the 0.8μm InAlAs/InAs MOS-HEMT
Fig. 6-4 Drain current (ID) versus gate-to-source voltage (VGS) curves of the 0.8μm InAlAs/InAs MOS-HEMT
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
0 5 10 15 20 25 0.0
0.2 0.4 0.6 0.8 1.0
Leakage current,I G(mA/mm)
VD(V) InAs MOS-HEMT
VG=0V , Lg=0.8m 0.8m*200m 0.8m*300m
Fig. 6-5 Gate-to-drain breakdown voltage (BVDG) of the 0.8μm InAlAs/InAs MOS- MHEMT
Fig. 6-6 Gate leakage current density performance of the 0.8μm -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
1E-9 1E-8 1E-7 1E-6
Leakage current,I G(A/device)
VG(V)
InAs MOS-HEMT VD=0.5V , Lg=0.8m
0.8m*50m 0.8m*200m 0.8m*300m 0.8m*500m
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Chapter7 Conclusions
In this study, 0.3μm InGaP/In0.22Ga0.78As PHEMTs, 0.8μm InAlAs/
In0.7Ga0.3As MOS-MHEMTs and 0.8μm InAlAs/InAs MOS-HEMTs were fabricated. The electrical characteristics of InGaP/In0.22Ga0.78As PHEMTs with different doping profiles were evaluated for both RF and digital application. On the device linearity issue, the uniformly-doped device shows higher IP3 of 22.19 dBm, and the channel doped device shows higher Δ (IP3-P1dB) of 14.23 dB, and higher IP3 to DC power consumption ratio (IP3/PDC) of 4.97 compared to other devices. Overall, the uniformly doped and channel doped devices have higher value of figure of merit for device linearity. From the aspect of digital application, SS and ION/IOFF ratio parameters can be improved by uniformly-doping in the Schottky layer and DIBL parameter can be reinforced by extra doping in the channel layer.
For high-speed digital application, the InGaAs channel with high indium concentration is required for better gate delay performance, and ALD Al2O3 was introduced as gate insulator to improve the insulating property. Both the 0.8μm InAlAs/In0.7Ga0.3As and InAlAs/InAs MOS-HEMTs demonstrate better insulating properties. Moreover, the digital parameters and threshold voltage didn’t vary with the various gate widths, leading to the possibility of InAlAs/In0.7Ga0.3As MOS-MHEMT employing air-bridge structure for digital utilization of different fan-out level.
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