2-1.1 Overview on DRAM Cell
Figure 2-1(a) shows a DRAM cell with one-transistor and one-capacitor (1T1C) structure, and Fig. 2-1(b) depicts one of the typical cell operations [35]. The cell data is read out to bit line (BL) while the selected world line (WL) is boosted to Vpp. After sensing, the BL voltage is fully amplified to internal array operation voltage Vaa for data
“1” and Vss for data “0” simultaneously. For data “1” write, the WL voltage must be higher than Vpp (=Vaa+Vtcell) to write data “1” to the memory cell, where Vtcell is the threshold voltage of the cell transistor. Besides, for data “0” write, the bit line must be biased to ground.
In the early age of DRAM development, two-dimensional cell structure, formed by double polysilicon transistor, was widely applied on the standard DRAM cell, known as the “planar type” DRAM. Three-dimensional cell structure was introduced to 4Mb-above generation, and these innovations included the trench capacitor cell and stacked capacitor cell (STC). Both of the trench and the stacked cell techniques are used
in commercial DRAM products till now, but they have been greatly improved in the past generations, as depicted in Figs. 2-2 (a) and (b) [36, 37]. The most important benefits of the trench cell are high transistor performance and effective topology.
Excellent transistor performance results from the trench capacitor formed at the early processing stage, so the thermal budget can be reduced during chip fabrication. Hence, it makes trench technology more favorable as the embedded memories integrated with the high performance CMOS logic [7]. The topology of trench can effectively raises the capacitance up, but without increasing the planar cell area. The disadvantages of trench cell come from the obstacles of the manufacture and the new material applications. The extremely deep trench etching and the cell isolation are very difficult to be manufactured by semiconductor processing technologies. In addition, the leakage current density of the trench capacitor rapidly increases as the cell size decreases due to lots of profile defects. Trench cell also lacks of fabrication technologies for high dielectric material applications, such as penta-oxide (Ta2O5) and barium strontium
Figure 2-1 (a) Schematic diagram of 1T1C-transistor cell in DRAMs. (b) Operation scheme and stress bias conditions [35].
World Line
titanate (BST).
On the other hands, the benefits of using the stacked cell (STC) are that the standard techniques of the planar silicon processing are still available for this capacitor fabrication, which is contained in the multiple interconnect layers above the silicon.
Therefore, lots of techniques can be applied on the stacked capacitor using the high dielectric materials. Stacked cell has been changed from the capacitor-under-bit line (CUB) to capacitor over bit line (COB) structure to increase the cell capacitance, as shown in Figs. 2-3 and 1-1 respectively. Compared with CUB, the COB stacked cell can
Figure 2-2 Schematic cross section of (a) stacked and (b) trench capacitor cell [7].
Figure 2-3 The schematic representation of the stacked cell using the typical structure of capacitor under bit-line (CUB) [3].
(b) (a)
provide larger cell area, so that will be a promised candidate for the giga-bit scaled DRAM. Although COB could be able to applied on giga-bit generation, there are still many challenges for scaling down, such as large leakage current at the storage junction, variation of cell transistors’ threshold voltage, parasitic resistance and capacitance between the bit-line/the cell-capacitor, and insufficient cell area. However, insufficient cell area is one of the most disadvantages for STC, so the high dielectric material is indeed necessary as the capacitor material for the new generation stacked-cell [3].
Memory cell capacitance plays a key role, which can determine the sensing signal margin, speed, data retention time and endurance against the soft error. In the multimega bit generation, the minimum cell capacitance should be 25 fF/cell. Capacitance can be described as the following equation.
A d
CS ε
×
= (2-1)
where CS is the memory cell capacitance, εis the capacitor dielectric, A denotes the capacitor area and d is the capacitor thickness. The leakage current at the cell node, consisted by sub-threshold leakage, irradiation charge loss, noise coupling, junction leakage and cell dielectric leakage, will strongly affect the sensing signal margin, as shown in the following equation.
)
where VS presents the sensing signal voltage, CB is the parasitic bit line capacitance, Ij, Isub and Id indicate the current of junction leakage, sub-threshold leakage and dielectric leakage. Tref is the refresh time, VN is the nose voltage owing to nose coupling and
transistor-threshold/sensing amplifier mismatch, and QC is the charge loss induced by irradiation [2]. To obtain the excellent properties of crystallinity and leakage reduction, the choice of electrode structure is another important concern. The trend of electrode-capacitor material structure is shown in Fig 2-4. The capacitor of COB cell adopted the silicon-insulator-silicon (SIS) structure before, but the novel Ta2O5 or Al2O3
dielectric in metal-insulator-silicon (MIS) is replacing the long-lived NO dielectric in SIS, ranging from 0.18μm to 100 nm node. As the feature size shrinking under 100 nm, the advanced high-K dielectric, Ex. BST, with metal-insulator-metal (MIM) will be inevitably applied on the giga-bit generation DRAM cell.
Ox or NO Poly Silicon
Poly Silicon
Ta2O5 or Al2O3 Metal
Poly Silicon
High-K Dielectric (BST) Nobel Metal
Nobel Metal Barrier & Adhesion Layer
SIS
MIS
MIM
0.18um above
0.18um ~ 100nm
New Generation
Figure 2-4 The evolvement trend of the multilayer structure used for DRAM cell capacitors.
2-1.2 Trend and Challenges of DRAM
In the past 20 years, the desktop PC was the primary driver for DRAM’s industry.
Although the PC market still keeps on growing, the DRAMs’ market structure must be modulated due to the high-end demand rising [38]. Fig. 2-5(a) indicates the memory sizes for the computer segment. In general, the communication servers require the highest density DRAM in each generation. Fig. 2-5(b) presents the
market trends of 128-megabit-equivalent DRAM.
Obviously, the market share of PCs’ DRAM are decreasing, but that of communications’ is greatly growing. The evolution of CMOS technologies was described as Moor’s law, which predicted the number of components would be double on the integrated circuit (IC) chip each year. The common rule of Moor’s law is still useful even though that has been modified several times [39]. The trend of lithographic capability was predicted by Semiconductor Figure 2-5 DRAM capacity requirement for
(a) average Mbytes/system by computer segment, and (b)major application demands [38].
Industry Association (SIA), as shown in Fig. 2-6(a), where half pitch is the minimum size of lithographic features on a chip. According to the experiential rule in the past 20 years, the chip density has been quadrupled every three years, and the chip size is 1.5X bigger than that of previous generation. In addition, the chip speed keeps on improving in spite of the chip size increasing. Table 1-1 shows the DRAM device requirements and overall technology trend. Fig. 2-6(b) shows the forecast of the chip-size/cell-size versus generation, based on the architecture of 8F2 folded line cell, where F is the feature size [4]. The vertical stack height is another important factor of COB technologies. To meet the requirement of minimum cell capacitance, dielectric thickness decreasing or stack height increasing are carried out as the solutions of the new generation cell, but both of them will induce large leakage current. The upper limitation trend of the stack height is shown in Fig. 2-6(c), which shows the stack height must be lower than 1μm to satisfy the 0.11μm technology and under [5].
The DRAM manufacturing was developed from 4Mb to 256Mb through the decade of the 1990s. During those generations, density-enhancing technologies dedicated in the shallow trench isolation (STI), bit-line contact borderless to world-line, capacitance enhancing, junction leakage suppressing and self-aligned buried strap [7]. A high substrate doping density, > 5×1017 /cm3, was required in order to keep the threshold voltage at 1 volt to suppress the short channel effect, but the junction leakage current would be the crucial issues due to this high doping density. Hence, the self-aligned channel implantation was introduced as the solution of substrate doping suppressed [2, 4]. The trend of cell transistor’s channel length is a function of substrate doping density, as shown in Fig. 2-7(a). In general, the minimum accepted cell capacitance is
Figure 2-6 Historical and future trends of (a) lithographic resolution capability, (b) cell sizes and chip sizes estimations based on the 8F2 folded bit line. (c) the maximum stack height of cylinder-type COB stack cell [4, 5, 39].
Figure 2-7 (a) Trend of channel length and substrate doping density of cell transistors. (b) Min cell capacitance as a function of substrate doping density.
(c) Data retention time as a function of DRAM density [4, 6].
(b) (a)
(c)
(b) (a)
(c)
reduced as the new generation progressing, but that must be higher than 25 fF /cell for the giga-bit DRAM cell. High doping density results in the junction leakage current increasing, so the cell capacitance must be higher than 25 fF /cell, as shown in Fig.
2-7(b). However, the requirements of the DRAMs’ cells from 1Mbit to 64Gbit are summarized in Table 1-1, which was further modified by the information of ITRS 2003 and IBM Res. [7, 8]. Besides, the data retention time is the one of the most important parameters for DRAMs’ applications. The data retention time is the period of the stored data lost owing to the leakage current before data refreshing. The data retention time has to be doubled as the memory density increases 4X in every new generation to satisfy the requirements of high speed and low power consumption, as shown in Fig. 2-7(c) [6].
The leakage current at a cell node, which was consisted by the cell transistor sub-threshold current, cell dielectric leakage and source/drain junction current, greatly influences the data retention time. Therefore, to obtain a better data retention property, the node leakage should be improved in many ways, such as interface improvement of shallow trench isolation, electric field suppressed at the cell node junction and material improvement in cell dielectric layer.
Year of the First
High-k Dielectric ONO or NO Bottom Electrode
Metal
Poly Silicon Metal Perovskite
Ta2O5, Al2O3 BST, STO Epi BST
Table 2-1 The solution roadmap of DRAM capacitor.
The selections of dielectric material and the electrode structure are very important for the electric properties of cell capacitor. Fig. 2-8 depicts the roadmap of capacitors’
material applied on various DRAMs’
generations [40]. The cell capacitor of the high density DRAM adopted
Si3N4/SiO2 (nitride/oxide, NO) as its insulator’s material under 256M-bit generation. Because the ultimate of NO dielectric is limited to around 4-nm in oxide equivalent thickness, the only possible solution is to increase surface area using hemi-spherical grain (HSG) technique.
However, there is not much room for the cell size scaling down owing to the limitations of the stack height and the HSG grain size. Therefore, a tantalum pentoxide (Ta2O5) is being applied on the generations of 256M-bit~4G-bit generation now instead of nitride material. The capacitor using Ta2O5 dielectric is based on metal-insulator-silicon (MIS) structure, but the capacitor structure will switch to metal-insulator-metal (MIM) structure for the generation scaling down to 0.13μm. The metal storage node instead of the poly silicon node is in order to eliminating the native oxide formed at the poly silicon node, but the technique of the metal electrode integrated with Ta2O5 dielectric is a big challenge due to large leakage current. So far, the Ta2O5 can be further scaled down to 0.13μm technology, but its limitation will be 2-3 nm in oxide equivalent
Figure 2-8 Trend of dielectric materials applied on various DRAM generations [40].
thickness. One of the prevalent candidate for multi-giga bit generation is probably (Ba, Sr)TiO3 (BST) dielectric, because BST can achieve extremely high dielectric constant around 150-400 and be crystallized on the noble metal electrode. MIM BST capacitor is the most promised cell capacitor in the near future. Table 2-1 indicates the roadmap of the cell capacitor development using different electrode structures and insulator material.
At current technology timeline, DRAM progressing is limited by further scaling-down of MOSFET channel length, leakage current and insufficient cell capacitance. As DRAM enters the 21st century, the advanced technologies ranging from 0.18μm to below 100nm give bright future for the new generation applications.