Silicon technology has been main basis of microelectronics and electronics systems for more than thirty years [1]. The performance and density of MOSFET integrated circuits are improved due to not only the progress in lithography but also the innovation in device fabrication technology. However, as device dimensions continue to be scaled down following the “Moore’s law”, the resistance of the polycrystal-line increases with the scaling factor. In addition, the increase of contact resistance is by the square of the factor. Those degradation due to the increase of parasitic resistance will give rise to excessive RC time delay and undesired voltage drop which may offset the advantages coming from the scaling technology or even deteriorate the performance of devices [2].
Over the years, many efforts have been made for reducing the parasitic resistance resulting from the device shrinking. Since 1966, metal silicides have been considerated for its advantages of low resistance and schottky contacts [3]. In 1979, the idea of metal silicides on the doped polysilicon for high-conductivity interconnect was proposed and adopted at once in industry [4]. Presently, this concept was extended into the diffusion region by the development of self-aligned silicide technology at both poly-gate and source/drain diffusion region [5]. Now, the
silicide-related technologies become integral module for the realization of nano-scale MOS devices.
The major advantages of metal silicides can be grouped as follows : (1) their low resistivity for gate and interconnect applications, (2) easy formation by self-aligned technology without any extra mask and compatible with conventional CMOS process, (3) silicides on S/D region can somewhat ease the problem of Al spiking. However, the main issue induced by silicides is the degradation on device reliability including the increase of junction leakage and the descent of oxide breakdown field [6, 7]. Thus, study on metal silicides process is essential for integration into the device fabrication processes.
For titanium silicide (TiSi2), it has been widely used in the IC industry due to its low sheet resistance (13-15Ω/ ) and high thermal stability.
However, it has been found that the sheet resistance of TiSi2 applied on poly-Si line will increase significantly as the line width scaled to the deep-submicron range (~0.2µm), i.e. the narrow line width effects. The increase in sheet resistance of narrow TiSi2 poly-Si line has been explained [8,9] in terms of the difficulty of the phase transformation from the high-resistance phase (C49-TiSi2 ~ 60-80Ω/ ) to the low-resistance phase (C54- TiSi2). Because the C54 structure features a large grain size (~0.2µm) compared with C49 structure [8-10]. Besides, the Ti diffusion will degrade the oxide reliability by trap generation even the silicidation temperature as low as 400oC [11].
Recently, CoSi2 is mostly used to be the alternative to TiSi2 due to its line-width independence characteristics [8]. In addition, th cobalt silicide
than TiSi2, better stability in presence of dopants and better resistance against plasma-etch [12]. However, its rough interface of silicide/Si and the relatively large Si consumption will restrict its application on poly-gate and on shallow junction due to the degradation on oxide reliability and the increase of junction leakage [13, 14].
Toward nano-scale device fabrication, NiSi is regarded as a potential candidate to replace TiSi2 and CoSi2. First, The sheet resistance of NiSi is comparable with that of TiSi2 and CoSi2. Another advantage of NiSi is its much more insensitive to the narrow line-width than TiSi2 and CoSi2. Besides, nickel silicide possesses the merits of lower formation temperature, less silicon consumption, only one annealing step, and relatively small film-stress compared with the other two silicides [15].
However, the major shortage for NiSi is its poor thermal stability. The appropriate improvement on thermal stability of NiSi will contribute to the integration into nano MOS device fabrication processes.
1.2 Motivation
Although NiSi has many advantages as mentioned, its poor thermal stability due to the formation of precipitates and NiSi2 will result in the degradation on device performance and reliability such as the increase of junction leakage. Thus, several efforts have been made for the improvement of its thermal charateristics.
Nitrogen ion implantation into the Si Substract prior to the deposition of Ni was reported to minimize the agglomeration of silicide and to widen
the window of silicide processing temperature. By the incorporation of nitrogen in Ni films, the roughness of the silicide/Si interface can be retarded [16] which leads to the improvement on the thermal stability of NiSi [16, 17]. However, it will sacrifice the sheet resistance for better thermal stability of NiSi.
Ti and TiN capping layer were introduced to reduce the junction leakage and enhance the thermal stability of NiSi by gettering oxygen and preventing the diffusion of oxygen, respectively [16, 18]. However, Ti may interdiffuse through Ni and form the TiSi2 or TixNySi. That will result in the increase of sheet resistance [19].
Furthermore, the insertion of a thin Pt layer and the addition of some amount of Pt was proposed to improve the thermal stability of NiSi due to the change in intrinsic quality [20].
In our experimental, we proposed a Zr cap on the Ni film to getter oxygen, which originated from the annealing ambient, the Ni-deposition chamber or interfacial oxide at metal/silion interface, because of the lower binding energy of Zr and O than that of Ti and O, and the better thermal stability of ZrSi. In order to integrate NiSi into the nano-scale device fabrication, NiSi is formed on 30nm ultra shallow junction, and is investigated for junction characteristics. Finally, full nickel silicide gate was accomplished and studied for future nano-device technology application.