Chapter 5 Conclusion
5.2 Future Works
5.2.3 High Profile Encoder
The latest extension of H.264, the scalable video coding, is in the final draft stage.
This extension is used to provide scalability of H.264 bit-stream so that the same bit-stream can be broadcasted to difference applications. And then, the different decoders retrieve the necessary data from the bit-stream. However, the foundation of the scalable video coding is the H.264 high profile codec. Therefore, we can use the H.264 high profile encoder as a basic structure and add the new coding tools of scalable video coding.
system with general purpose processor and external memory system. Therefore, in addition to the chip performance, we should consider the integration of our design.
Therefore, we are implementing a FPGA platform which implements our design into FPGA as an IP in an embedded system. By this platform, we can evaluate the system performance of a complete H.264 encoding system and modify our chip design to fit the requirement of whole system.
z H.264 High Profile Encoder with Rate-Distortion Optimization (RDO)
H.264 standard supports rate-distortion optimization technique to further improve the video quality and reduce the bit-rate. However, the iterative coding flow of rate-distortion optimization results in multiple times of complexity than that of encoder without optimization. Besides, the iterative loops also result in data hazard in pipelined system architecture. Therefore, most of H.264 encoder implementations don’t include the rate-distortion optimization technique. However, the benefits of RDO is more obvious for high definition video application which pursuits the best video quality and optimized compression rate. So it is necessary to include the RDO function in future encoder design.
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作者簡歷
姓名 林佑昆 英文姓名 Yu-Kun Lin
性別 男 生日 1979/5/22
出生地 高雄市 電子信箱 [email protected].
nctu.edu.tw
學歷
學位 學校 系所 在學期間
學士 國立台灣大學 電機工程學系 1996/9~2000/7
碩士 國立台灣大學 電機工程學研究所 2000/9~2002/7
博士 國立交通大學 電子研究所 2002/9~2008/7
經歷
交通大學電子所VLSI Signal Processing Lab.
系統管理員
晶片系統設計中心(CIC)約聘人員 矽智產設計課程助教
計算機結構課程助教
電子系統層級設計課程助教
2002/9~2005/6 2004/9~2005/6 2004/9~2005/1 2005/2~2005/6 2006/2~2006/6
專長
1. Digital IC design flow (from RTL to gdsII) 2. Silicon IP design methodology
3. Video codec (MPEG 1/2/4, H.264, Scalable Video Coding) 4. Digital image processing
5. VLSI signal processing 6. Computer architecture
7. Electric system level design
8. ARM-based system platform design 9. Biomedical electronics
榮譽
學業成績優良 1. 大一上 書卷獎 全系第一名
2. 碩士班一年級 全組第一名
3. 碩士班二年級 A 類助學金(全組前 10%) 4. 91 年度斐陶斐榮譽會員
5. 交大博士班獎學金兩年(博士班前五名入學)
研究成果獲獎 1. 92 學年度教育部 IP 設計競賽優勝
2. ASP-DAC 2005 Design Contest Winner
3. 45th ISSCC/DAC Student Design Contest Winner 4. 獲頂尖會議 DAC 2008 邀稿
5. 指導大學部專題生獲 Tensilica 2005 Xtensa 可配 置式處理器設計大賽 第一名
6. 2008 年交大電子所博士論文獎 優等獎
社團領導 1. 87年度台大優良服務性社團負責人 – 華南慈善
獎學金
作者著作目錄
International Journal Papers:
[1] Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, and Tian-Sheuan Chang, "A Hardware Efficient H.264/AVC Motion Estimation Design for High Definition Video," to be published, IEEE Transaction on Circuit and System I: Regular Papers.
[2] Yu-Kun Lin, Chun-Wei Ku, De-Wei Li, and Tian-Sheuan Chang , “A 140MHz 94K GATES HD1080P 30 FRAMES/SEC INTRA-ONLY PROFILE H.264 ENCODER,” to be published, IEEE Transaction on Circuit and System for Video Technology.
International Conference Papers:
[1] Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, and Tian-Sheuan Chang, “A 242mW, 10mm2 1080p H.264/AVC High Profile Encoder Chip,” to be published, Design Automation Conference (DAC), June 2008. (Invited Paper)
[2] Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, and Tian-Sheuan Chang, “A 242mW, 10mm2 1080p H.264/AVC High Profile Encoder Chip,” International Solid-State Circuits Conference (ISSCC), pp. 314-315, Feb. 2008.
[3] Chia-Chun Lin, Yu-Kun Lin, and Tian-Sheuan Chang, “Hardware Efficient Skip Mode Detection for H.264/AVC,” International Conference on Consumer Electronics (ICCE), Jan., 2008.
Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 1, pp. 1185- 1188, April 2007,.
[5] Jian-Long Chen, Yu-Kun Lin, and Tian-Sheuan Chang, "A Low Cost Context Adaptive Arithmetic Coder for H.264/MPEG-4 AVC Video Coding," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP),
vol.2 pp. 105-108, April 2007.
[6] Chia-Chun Lin, Yu-Kun Lin, and Tian-Sheuan Chang, "PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 2, pp. 385-388, April 2007.
[7] De-Wei Li, Chun-Wei Ku, Chao-Chung Cheng, Yu-Kun Lin, and Tian-Sheuan Chang, "A 61MHz 72K Gates 1280X720 30FPS H.264 Intra Encoder," IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP),
vol.2, pp. 801-804, April 2007.
[8] Chia-Chun Lin, Yu-Kun Lin, and Tian-Sheuan Chang, "A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),pp. 1248-1251, Dec.
2006.
[9] Tzu-Yun Kuo, Yu-Kun Lin, and Tian-Sheuan Chang, "A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding,"
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1244-1247,
Dec. 2006.
[10] Jia-Bin Huang, Yu-Kun Lin, and Tian-Sheuan Chang, "A Display Order Oriented Scalable Video Decoder," IEEE Asia Pacific Conference on Circuits and
[11] Yu-Kun Lin and Tian-Sheuan Chang, "Analysis and architectures of MCTF for scalable video coding," Picture Coding Symposium (PCS), May 2006.
[12] Yu-Kun Lin and Tian-Sheuan Chang, "Fast block type decision algorithm for intra prediction in H.264 FRext," in IEEE International Conference on Image Processing (ICIP), pp. 585-588, Sep. 2005.
[13] Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, and Tian-Sheuan Chang, "A Bandwidth Efficient Subsampling-based Block Matching Architecture for Motion Estimation," Asia and South Pacific Design Automation Conference (ASP-DAC), vol.
2, pp. D/7 - D/8, Jan. 2005.
Domestic Conference Papers:
[1] Yu-Kun Lin, Ying-Ze Liao, and Tian-Sheuan Chang, “AN AREA-EFFICIENT DESIGN FOR INTEGER TRANSFORM IN H.264/AVC FRExt,” VLSI Design/CAD Symposium, pp. 517-520, Aug. 2006.
[2] Chia-Chun Lin, Yu-Kun Lin, and Tian-Sheuan Chang, “Hardware Oriented Algorithms for Motion Estimation in MPEG-4 AVC/H.264 Video Coding, “ VLSI Design/CAD Symposium, , pp. 505-508, Aug. 2006.