INTEGRATOR

An overall circuit of the integrator is shown in Fig.3.5. It is made up of fully differential opamp and common-mode feedback circuit.

OP2

Fig.3.5. Integrator architecture

In order to operating in high-speed and obtaining noise-shaping benefit the opamp gain and bandwidth need to consider.

Finite op-amp gain causes the inverting op-amp terminal to reflect the output voltage rather than behave as a virtual ground. Not all of the charge will be transferred to the integrating capacitor, resulting in a “leaky” integration.

The output of the SDM, v(kT), is the sum of the previous output, v(kT-T), and the previous input, u(kT-T):

(9)

The constant represents the gain preceding the input to the integrator. The above equation corresponds to the following transfer function for an ideal integrator:

(10)

The dc gain of the ideal integrator is infinite. In practice, the gain is limited by )

circuit constraints. The consequence of this “integrator leak” is that only a fraction of of the previous output of the integrator is added to each new input sample.

(11)

And the dc gain is . The limited gain at low frequency reduces the attenuation of the quantization noise in the baseband, results in an increase of the in-band quantization noise that is given by

(12)

M is oversampling ratio, the performance penalty incurred is on the order of 1dB when the integrator dc gain is comparable to the oversampling ratio as shown in Fig.3.6.

Fig.3.6. Influence of integrator leak on baseband quantization noise

1

integrators should have

(13) [20]

Normally, the designers will typically ensure that the opamp gain is at least

oversampling ratio, If this holds, the SNR will be only about 1dB worse than if the integrators had infinite gain. In the thesis the OSR=256, then the opamp DC gain is about 48dB.

For an amplifier with a single dominant pole and unity-gain frequency fu, the impulse response of the integrator output during sampling will be exponential with a time constant [22],[23]

(14) must be met in order to guarantee stability of the modulator. This requirement corresponds to a lower limit for fu of

(15) The fact that only one-half of the clock period T is available for the integration.

And the opamp bandwidth could be as low as fs, the sampling frequency, give negligible performance loss [20].

The simulation results indicate a sharp increase in both quantization noise and

harmonic distortion of the converter when the slew rate is less than as shown in Fig3.7. Δis the difference between adjacent quantizer output levels. These simulations are

OSR

response is exponential with time constantτ:

(16) the term has been included to separate the effects of finite slew rate from those due to variation in the equivalent gain. The peak rate of change in the impulse response occurs at t=0 and is given by

(17) Slewing distortion occurs when this rate exceeds the maximum slew rate the integrator can support [20].

Fig.3.7. Simulated influence of integrator output slew rate on baseband quantization noise[20]

The Settling time of the opamp has 0.01% accuracy that is about 13.2b resolution accuracy. In the thesis, the accuracy is 0.04% needed. So the specification is met.

Fig.3.8 show the only one stage amplifier op-amp circuit, the open- loop gain is 26.4dB, bandwidth is 42MHz as shown in Fig.3.9, phase margin, gain margin is limited by R1 ,R2,C1,C2 in common-mode feedback circuit.

To achieve the specification requirement, the two stages structure is needed.

VIN+

VIN-M1 M2 M3 M4

M9 M10 M11 M12

M13 M14 M15 M16

VOUT+

Bias2:1.65V CMFB

Fig.3.8. Fully differential opamp circuit only one stage amplifier

Fig.3.9. Only one stage opamp, the open-loop gain is 26.4dB, bandwidth is 42MHz

M13 M14 M15 M16 M17 M18

VOUT+

Fig.3.10. Fully differential opamp circuit used in integrator

The fully differential opamp, which has two-cascade-stage topology compensated by

stage, and the second pole is located at the output of second stage as follows:

The open-loop dc gain (Av), the unity gain bandwidth (?u) and the slew-rate are as follow, A_V = g_m11(r_o11//r₀₃)g_m7(r_o7//r_o5)≈ g_m²r_o² (20)

The second-pole is moved to higher frequency. Therefore the bandwidth of this opamp is increased and there is no other non-dominant pole to limit the bandwidth. Moreover, only a dominant pole and second pole exist in the signal path, the frequency compensation is easy to design and achieve. Also, the simple second-stage topology allows large output signal swings of 1.4V peak-to-peak differential from a 2.5V supply voltage without linearity degradation.

Though, the open-loop dc gain is about gm2

ro2

. Only 48dB of open- loop dc gain is required for 11b resolution. From above analysis, therefore, the open- loop dc gain and reducing flicker noise can be achieved easily by using the long channel of MOS (M3~M6) and the larger parasitic capacitance combined to the dominant pole does not limit the bandwidth. Another drawback of the opamp is the common mode feedback circuits are

required on each stage.

Typically, when using fully differential opamps in a feedback application, the applied feedback determines the differential signal output voltages, but the output common mode voltages are not well-defined. It is necessary to add additional circuit to keep the output common mode voltage of opamp constant and to control it to be equal to some specified voltage. The additional circuit is referred to as the common-mode feedback circuit (CMFB).

The fully differential opamp, the output common- mode voltages of both stages are undefined. Therefore, the opamp uses two CMFB circuits, one for each stage. For the first-stage of the opamp, the CMFB circuit is done by simply connecting the node (CMFB1 node) at the drain of M17 and M18 to the gate of M16 as shown in Fig.3.10. The voltage on node CMFB1 is

M15 M16 M17 M18

VOUT+

Fig.3.11. Common-mode feedback circuit used in integrator [4] [7]

where if the current in the second-stage of opamp is fixed, the voltage on node CMFB1 can sense the output common-mode voltage of first-stage of this opamp. When the common-mode voltage of Voutp, Voutn is too high so does the voltage on node CMFB1. By connecting the node CMFB1 to gate of M16, the gate voltage of M16 goes up and then decreases the

common-mode voltage back to the desired output common-mode voltage (Vocm1). The desired output common-mode voltage is (Vgs7, 8+Vgs16).

For the second-stage of opamp, An alternative approach for realizing common- mode feedback circuit is shown in Fig.3.11 [4] [7]. This circuit generates common-mode voltage of the output signals at node VA. This voltage is compared to bias2 using a separate amplifier.

The voltage at node CMFB2 is connected to gate of M18 of the fully differential opamp so that the common- mode voltage of the fully differential opamp output is the fixed. The voltage of the VA and Bias2 needed to satisfy the following equation:

To ensure common- mode stability, the NMOS current sources (M15,M16) and (M17,M18) are split into two, the reduced gm increases the phase margin of the CMFB loop and improves the common-mode stability.

The voltage of CMFB1 is 0.609V, CMFB2 is 0.643V. The current of the M15 is 2

45uA , M16 is 236uA, M17 is 184uA, M18 is 740uA. The current source is dominated by M16 and M18.

Table I. The fully differential opamp characteristic

VDD 2.5V

Open-loop gain 74.5dB

fu@6pF load 110MHz

Phase margin 54 degree

Gain margin 35dB

Slew rate 17.5V/us

Settling time 29.3ns

CMRR@44KHz 131.2dB

Input common-mode range 0.7~2V

Output swing 1.4V