CHAPTER 2 ARCHITECTURE DESIGN AND OPERATING PRINCIPLE
2.2 DIGITAL DECIMATION FILTER
Filtering noise, which could be aliased back into the baseband, is the primary purpose of the digital filtering stage. Its secondary purpose is to take the 1-bit data stream that has a high sample rate and transforms it into an n-bit (n>>1) data stream at a lower sample rate. This process is known as decimation. Essentially, decimation is both an averaging filter function and a rate reduction function performed simultaneously.
Three basic tasks are performed in the digital filter sections:
1. Remove shaped quantization noise: The Sigma-Delta modulator is designed to suppress quantization noise in the baseband. Reducing the baseband quantization noise is equivalent to increasing the effective resolution of the digital output. The most of the quantization noise is at frequencies above the baseband. The main objective of the digital filter is to remove this out-of-band quantization noise.
2. Decimation (sample rate reduction): The output of the Sigma-Delta modulator is at a very high sampling rate. After the high frequency quantization noise is filtered out, it is desirable to bring the sampling rate down to the Nyquist rate, which minimizes the amount of information for subsequent transmission, storage, or digital signal processing.
3. Anti-aliasing: When the digital processor reduces the sampling rate down to the Nyquist rate, it needs to provide the necessary additional aliasing rejection for the input signal as
opposed to the internally generated quantization noise.
The simplest and most economical filter to reduce the input sampling rate is a
“Comb-Filter”, because such a filter does not require a multiplier. The remaining filtering is performed in three stages using half-band filters, which implement 2:1 decimation and have linear phase characteristic.
Because of the entirely different quantization process of Sigma-Delta ADCs, performances of theses ADCs can’t be described in terms of integral and differential nonlinearity as in the case of Nyquist rate ADCs. Instead, performance measures such as signal-to-noise ratio (SNR) can be used to evaluate the effective number of bits (ENOB).
(4)[11]
(5)
DR is dynamic range; L is bit number of the quantizer, in the thesis is one. And the dynamic range of a B-bit Nyquist rate ADC is
How to trade-off the order number as shown in follow:
1. To decide the in-band frequency fb.
2. To decide the resolution of the ADC, the DR² can be calculated by equation (5) . 3. And from equation (4) if L (order)=1,can calculate OSR, then the fs is known.
1
4. If the higher fs is needed, the circuit is difficult to implement, can try L (order)=2, then the lower fs is got, the circuit is easier to implement.
In the thesis, OSR=256, from equation (4) (5) can obtain B is 11.1b resolution, DR(dB) =68.6dB.
CHAPTER 3
CIRCUIT IMPLEMENTATION
3.1 ANALOG CIRCUIT REALIZATION
The analog circuit of the first-order sigma-delta modulator is made up of fully differential Gm Amplifier, Integrator and 2-level Quantizer, is shown in Fig.3.1. Fully
differential circuits achieve better power supply rejection and common mode noise rejection.
COMP
VI+
VI-fs Gm
IO+
IO-2fs
2fs RTZ DAC+
RTZ
DAC-integrator
quantizer
Fig.3.1. First-order sigma-delta modulator architecture
3.1.1 GM AMPLIFIER
In order to operating in high-speed operation the current-steering [1] and current- mode with 1/4 clock delayed 2- level return-to-zero (RTZ) feedback techniques [3] is adapted. Firstly, in order to designing a linear Gm amp is to use a triode-region transistor as shown in Fig.3.2 [4]. The cascade and gain boost structure provides large output impedance and high-swing cascade-current-source load to the Gm amp. The output cross-coupling connection reduces the common- mode gain of the Gm amplifier. Fig.3.3. show the circuit of the opamp used in the Gm amp, has 78 dB open loop gain and 114 MHz bandwidth [11]. The current of the triode-region transistor is shown in equation (6). And the transconductance of the Gm amp is shown in equation (7).
(6)
(7)
Where µn is mobility of n-channel MOS, Cox is oxide capacitance, the gm value is proportional to Vds.
ds
Vdd
M13 M14 M15 M16
70/1
Fig.3.2. Fully differential triode-region Gm amp [4] [5]
Vdd
Fig.3.3. Opamp circuit used in the Gm amp
The opamp show in Fig.3.3 serves two functions. Firstly, it is used to control the Vds of the transistor (M1, M2, M3, M4) to be equal to bias2, so that the gm can be proportional to a constant voltage bias2. The reference voltage bias2 should smaller than (Vgs-Vt) of M1, M2, M3, M4 in order to enforce the transistor to operate in the triode-region.
Secondly, it is used to enhance the output impedance of the Gm amp. The gain of the opamp should be reasonable large, so that the Vds of the triode-region transistor can follow the control bias2 as close as possible.
To create a negative feedback path is only for common- mode signals. For differential signals, CMFB has no effect on circuit performance.
An alternative approach for realizing common- mode feedback circuit is shown in Fig.3.4 [4] [7]. C1, C2 is compensation capacitor, to stable the differential loop. It is used in the Gm amp. This circuit generates common- mode voltage of the output signals at node VA.
This voltage is compared to bias2 using a separate amplifier. The voltage at node CMFB1 is feedback to the Gm amp so that the common- mode voltage of the Gm amp output is the same.
The voltage of the VA and Bias4 needed to satisfy the following equation:
(8)
4= = IO++2IO− VA
Bias
Vdd
M13 M14 M15 M16
70/1 Fig.3.4. Common-mode feedback circuit used in the Gm amp [4] [7]
The first transconductor in the continuous-time SDM is most important for overall thermal noise and linearity. A mismatch in the input differential pair transistors leads to an offset which results in a dc term in the output spectrum; where dc is not removed by the decimation.
3.1.2 INTEGRATOR
An overall circuit of the integrator is shown in Fig.3.5. It is made up of fully differential opamp and common-mode feedback circuit.
OP2
Fig.3.5. Integrator architecture
In order to operating in high-speed and obtaining noise-shaping benefit the opamp gain and bandwidth need to consider.
Finite op-amp gain causes the inverting op-amp terminal to reflect the output voltage rather than behave as a virtual ground. Not all of the charge will be transferred to the integrating capacitor, resulting in a “leaky” integration.
The output of the SDM, v(kT), is the sum of the previous output, v(kT-T), and the previous input, u(kT-T):
(9)
The constant represents the gain preceding the input to the integrator. The above equation corresponds to the following transfer function for an ideal integrator:
(10)
The dc gain of the ideal integrator is infinite. In practice, the gain is limited by )
circuit constraints. The consequence of this “integrator leak” is that only a fraction of of the previous output of the integrator is added to each new input sample.
(11)
And the dc gain is . The limited gain at low frequency reduces the attenuation of the quantization noise in the baseband, results in an increase of the in-band quantization noise that is given by
(12)
M is oversampling ratio, the performance penalty incurred is on the order of 1dB when the integrator dc gain is comparable to the oversampling ratio as shown in Fig.3.6.
Fig.3.6. Influence of integrator leak on baseband quantization noise
1
integrators should have
(13) [20]
Normally, the designers will typically ensure that the opamp gain is at least
oversampling ratio, If this holds, the SNR will be only about 1dB worse than if the integrators had infinite gain. In the thesis the OSR=256, then the opamp DC gain is about 48dB.
For an amplifier with a single dominant pole and unity-gain frequency fu, the impulse response of the integrator output during sampling will be exponential with a time constant [22],[23]
(14) must be met in order to guarantee stability of the modulator. This requirement corresponds to a lower limit for fu of
(15) The fact that only one-half of the clock period T is available for the integration.
And the opamp bandwidth could be as low as fs, the sampling frequency, give negligible performance loss [20].
The simulation results indicate a sharp increase in both quantization noise and
harmonic distortion of the converter when the slew rate is less than as shown in Fig3.7. Δis the difference between adjacent quantizer output levels. These simulations are
OSR
response is exponential with time constantτ:
(16) the term has been included to separate the effects of finite slew rate from those due to variation in the equivalent gain. The peak rate of change in the impulse response occurs at t=0 and is given by
(17) Slewing distortion occurs when this rate exceeds the maximum slew rate the integrator can support [20].
Fig.3.7. Simulated influence of integrator output slew rate on baseband quantization noise[20]
The Settling time of the opamp has 0.01% accuracy that is about 13.2b resolution accuracy. In the thesis, the accuracy is 0.04% needed. So the specification is met.
Fig.3.8 show the only one stage amplifier op-amp circuit, the open- loop gain is 26.4dB, bandwidth is 42MHz as shown in Fig.3.9, phase margin, gain margin is limited by R1 ,R2,C1,C2 in common-mode feedback circuit.
To achieve the specification requirement, the two stages structure is needed.
VIN+
VIN-M1 M2 M3 M4
M9 M10 M11 M12
M13 M14 M15 M16
VOUT+
Bias2:1.65V CMFB
Fig.3.8. Fully differential opamp circuit only one stage amplifier
Fig.3.9. Only one stage opamp, the open-loop gain is 26.4dB, bandwidth is 42MHz
M13 M14 M15 M16 M17 M18
VOUT+
Fig.3.10. Fully differential opamp circuit used in integrator
The fully differential opamp, which has two-cascade-stage topology compensated by
stage, and the second pole is located at the output of second stage as follows:
The open-loop dc gain (Av), the unity gain bandwidth (?u) and the slew-rate are as follow, AV = gm11(ro11//r03)gm7(ro7//ro5)≈ gm2ro2 (20)
The second-pole is moved to higher frequency. Therefore the bandwidth of this opamp is increased and there is no other non-dominant pole to limit the bandwidth. Moreover, only a dominant pole and second pole exist in the signal path, the frequency compensation is easy to design and achieve. Also, the simple second-stage topology allows large output signal swings of 1.4V peak-to-peak differential from a 2.5V supply voltage without linearity degradation.
Though, the open-loop dc gain is about gm2
ro2
. Only 48dB of open- loop dc gain is required for 11b resolution. From above analysis, therefore, the open- loop dc gain and reducing flicker noise can be achieved easily by using the long channel of MOS (M3~M6) and the larger parasitic capacitance combined to the dominant pole does not limit the bandwidth. Another drawback of the opamp is the common mode feedback circuits are
required on each stage.
Typically, when using fully differential opamps in a feedback application, the applied feedback determines the differential signal output voltages, but the output common mode voltages are not well-defined. It is necessary to add additional circuit to keep the output common mode voltage of opamp constant and to control it to be equal to some specified voltage. The additional circuit is referred to as the common-mode feedback circuit (CMFB).
The fully differential opamp, the output common- mode voltages of both stages are undefined. Therefore, the opamp uses two CMFB circuits, one for each stage. For the first-stage of the opamp, the CMFB circuit is done by simply connecting the node (CMFB1 node) at the drain of M17 and M18 to the gate of M16 as shown in Fig.3.10. The voltage on node CMFB1 is
M15 M16 M17 M18
VOUT+
Fig.3.11. Common-mode feedback circuit used in integrator [4] [7]
where if the current in the second-stage of opamp is fixed, the voltage on node CMFB1 can sense the output common-mode voltage of first-stage of this opamp. When the common-mode voltage of Voutp, Voutn is too high so does the voltage on node CMFB1. By connecting the node CMFB1 to gate of M16, the gate voltage of M16 goes up and then decreases the
common-mode voltage back to the desired output common-mode voltage (Vocm1). The desired output common-mode voltage is (Vgs7, 8+Vgs16).
For the second-stage of opamp, An alternative approach for realizing common- mode feedback circuit is shown in Fig.3.11 [4] [7]. This circuit generates common-mode voltage of the output signals at node VA. This voltage is compared to bias2 using a separate amplifier.
The voltage at node CMFB2 is connected to gate of M18 of the fully differential opamp so that the common- mode voltage of the fully differential opamp output is the fixed. The voltage of the VA and Bias2 needed to satisfy the following equation:
(24)
To ensure common- mode stability, the NMOS current sources (M15,M16) and (M17,M18) are split into two, the reduced gm increases the phase margin of the CMFB loop and improves the common-mode stability.
The voltage of CMFB1 is 0.609V, CMFB2 is 0.643V. The current of the M15 is 2
45uA , M16 is 236uA, M17 is 184uA, M18 is 740uA. The current source is dominated by M16 and M18.
Table I. The fully differential opamp characteristic
VDD 2.5V
Open-loop gain 74.5dB
fu@6pF load 110MHz
Phase margin 54 degree
Gain margin 35dB
Slew rate 17.5V/us
Settling time 29.3ns
CMRR@44KHz 131.2dB
Input common-mode range 0.7~2V
Output swing 1.4V
3.1.3 QUANTIZER
In sigma-delta modulators, the comparator is required to work at high oversampling frequency but its resolution can be as small as 1-bit. Therefore, the comparator design in sigma-delta modulators focuses more on a high-speed operation instead of accuracy.
3.1.3.1 COMPARATOR DESIGN
To combine the sample-and-hold function and the comparator function in a quantizer, the latch-type comparator is adapted. Another reason is it operates in
high-speed .The schematic of the latch-type comparator is shown in Fig.3.12. The operation of the comparator is described as follows:
During the pre-charge phase, i.e. when latch goes low, transistors M5 and M6 are turn off and the comparator does not respond to any input signal. The voltages Voc+ and Voc- will be pulled to Vdd, and the output of the inverters will be pulled to ground. At the same time, M1 and M4 discharge the voltages Vf+ and Vf- to ground.
During the evaluation phase, i.e. when latch goes high, both the voltages Voc+ and Voc- drop from Vdd and both the voltages Vf+ and Vf- rise from ground initially. If the voltage at Vi+ is higher than that at Vi-, M1 draws more current than M4. Thus, Voc+ drops faster than Voc- and Vf- rises faster than Vf+. As Voc+ drops to Vdd-Vtp, M9 turns on and charge Voc- to high level while Voc+ keeps going to ground. Also, as Vf- rises to Vtn, M2 turns on and discharge Vf+ to ground while Vf- keeps rising to Vdd.
The regenerative action of M8 and M9 together with that of M2 and M3 pulls Voc+
to ground and pulls Voc- to Vdd. Hence, following the inverters M11-M14, Vo+ is pulled to Vdd and Vo- is pulled to ground. The operation for the case when the voltage at Vi- is higher than that at Vi+ is similar.
VIN+
Fig.3.12. Latch-type comparator [5]
The digital circuit generating the DAC controls signals with high-crossing and low-crossing points, as shown in Fig.3.13, waveform is shown in Fig.3.14. In order to reduce the clock jitter on the control signals, the inverters driving the DAC switches are supplied from the analog Vdd. Fs is generated by 2Fs signal through the divided 2 circuit. The DAC control signals (RZP. RZN.P-.N+.P+.N-) with ¼ duty RTZ are generated by 2Fs.
To reach the high-speed operation and 1/4 latch cycle RTZ, the dummy loop is made up by M2, M5, M8, M11. The signals controlling the NMOS switches (RZN, N+, and N-) have a high crossing point. In the same way, the PMOS switches control signals (RZP, P+
and P-) have a low crossing point. The DAC circuit is illustrated in Fig.3.15.
D
Fig.3.14. Timing diagram of high-crossing NMOS-switch control signals and low-crossing PMOS-switch control signals [6].
Fig.3.15. DAC circuit [6]
The mismatch of Iref+ and Iref- can result in lower Performance as shown in Fig.3.16. The layout is needed to consider between Iref+ and Iref- relative mismatch.
Vdd
3.1.3.2 RETURN-TO-ZERO (RTZ) FEEDBACK DAC CIRCUIT
When the RTZ is larger than 55%, it can reduce the performance in the thesis as shown in Fig.3.17. The RTZ time is needed to larger than loop delay, but cannot too long.
Otherwise, it can affect the modulation result.
Fig.3.17. The effect of RTZ duty
An external clock frequency equal to twice the sampling frequency is required in order to get a T/4 RTZ phase at the beginning of each cycle as shown in Fig.3.18. The output current is directed either to IDAC+ or IDAC- depending on the comparator output DATA.
During RTZ phase, the positive and negative current sources are connected together through the Bias3 node. IDAC+ and IDAC- are voltage-control-current-source, P+=P-=Vdd, N+=N-=0, its current is zero Amp. It has no offset occurred during the return-to-zero (RTZ) interval.
In addition to reducing errors due to comparator delay and DAC output waveform asymmetry.
The purpose of cascading the switch transistor is to:
1. Reduce the capacitance seen by the output node (the input of the integrator and the output of the Gm amp). This reduces error current due to charging of the drain of the current source transistor to the potential of the output node.
2. Prevent any voltage variations at the output from reaching the drain of the current source transistor.
3. Increase the output resistance of the current source.
4. Prevent glitches that occur during switching from reaching the output through of the switch transistor.
Circuit noise is usually the performance-limiting factor; include KT/C noise in capacitors, thermal noise in the resistors and switches, 1/f noise in the MOSFETS.
3.2 DIGITAL DECIMATION FILTER SIMULATION BY MATLAB
Filtering noise, which could be aliased back into the baseband, is the primary purpose of the digital filtering stage. Its secondary purpose is to take the 1-bit data stream that has a high sample rate and transform it into an n-bit data stream at a lower sample rate. This process is known as decimation. Essentially, decimation is both an averaging filter function and a rate reduction function performed simultaneously.
A multistage decimation filter is shown in Fig.3.19. It is made up second order comb-filter and three stages half-band filter. Comb filters are suitable for reducing the sampling rate to eight times the Nyquist rate. The remaining filtering is performed in three stages FIR filters.
3.2.1 COMB FILTER
The simplest and most economical filter to reduce the input sampling rate is a
“Comb-Filter”, because such a filter does not require a multiplier. Because of the comb-filter coefficients are all unity. This comb-filter operation is equivalent to a rectangular window finite impulse response (FIR) filter.
The transfer function H (z) of a Comb Filter of order k for a decimation ratio N is defined by
(25) in the thesis, the order M=1 and decimation ratio N=32.
Fig.3.20. Block diagram of one-stage Comb Filtering process