→g + −→g−→x = 0 (4.6)
−
→zj − −→z j+1 = λ−→x (4.7)
where λ is selected such thatgk+1 < gk, but is as close as possible to 1. It handles the error by computing an error function that can be defined by two methods.The Newton iterations stop if the convergence criteria are fulfilled. One convergence criterion is the norm of the right-hand side, that is,g in Eg. 4.6. Natural criterion may be the relative error of the variables measured, such as(λx)z .
4.4 Illustration Examples
We now present numerical results to demonstrate effect of the proposed physical model and performance of the adaptive computing technique in poly-Si TFTs’ simulation. As shown in Fig. 3.1, the simulated TFT device is with aj = 4 μm, be = gi = 1 μm, and ac = hj
= 0.5 μm. The gate oxide thickness of the SiO2 layer is equal to 100 nm. The junction depth is with bc = hi = 0.05 μm. The channel length df = eg = 2μm. The 0.3 μm grain size is considered in this work [54, 64]. Hence, there are ten grain boundaries along the direction of channel. The poly-Si TFTs are assumed to have an elliptical-shaped Gaussian doping profile, where the peak concentration is equal to 2∗ 1020cm−3. Fig. 4.3 shows the
4.4 : Illustration Examples 45
Figure 4.3: An illustration of the doping profile used in the numerical simulation of poly-Si TFTs.
used spatial-dependent doping profile D(x, y) in the poly-Si TFTs simulation. Figs. 4.4 show the process of mesh refinements. The mechanism of 1-irregular mesh refinement is based on the estimation of solution error element by element. Fig. 4.4(a) is the initial mesh which contains 25 nodes, Fig. 4.4(b) is the 4threfined mesh containing 729 nodes, and Fig.
4.4(c) contains 3868 nodes is the 7thmesh. We note that the process of mesh refinement is guided by the result of error estimation automatically. As shown in Fig. 4.4(c), at the 7th refined level we find that most of refined meshes are intensively located near the surface
46 Chapter 4 : Solution Techniques
of channel and the junction of the drain side due to large variation of the solution gradient.
The distribution of refined mesh is consistent with the profile of computed electrostatic po-tential, shown in Fig. 4.5. The number of nodes (and elements) versus the number of levels of mesh refinement is shown in Fig. 4.6. The simulations are with and without including the nonlinear trap model to account for the effect of grain boundary. The number of refined elements and nodes is increased as the refinement levels are increased. At the beginning, the number of refined nodes (and elements) is increased fast due to significant variations of computed solution. After several refinements and solution processes, the increasing rate of the number of nodes (and elements) gradually becomes slow when the refinements are increased. It eventually reaches to a saturated condition.
Fig. 4.7 shows the convergence behavior of Gummel’s (outer) and Newton’s method (inner) when solving the electrostatic potential with and without including the trap model of grain boundary in the simulated TFT device. Here, we also defined an additional linear trap model of grain boundary by setting BT (φ) = NT A. The biasing conditions in all sim-ulation cases are VD = 1.0 V and VG= 1.0 V . The stopping criteria for the inner and outer iteration loops are 1e− 6 and 1e − 3, respectively, for all computed physical quantities.
We found that the case of DD simulation without considering any trap models converges quickly among three testing cases. However, the cases of DD simulation with the linear and nonlinear trap models of grain boundary have a similar convergence behavior.
4.4 : Illustration Examples 47
(a)
(b) (c)
Figure 4.4: (a) The initial mesh used for starting the solution process, (b) the 4threfined 1-irregular mesh which contains 729 nodes, and (c) the 7th refined mesh which contains 3868 nodes.
48 Chapter 4 : Solution Techniques
Figure 4.5: The simulated electrostatic potential at the 7thlevel. The poly-Si TFT is biased at VD = VG= 1.0V .
4.4 : Illustration Examples 49
Figure 4.6: The number of nodes and elements versus the refinement levels with and without considering the trap models of grain boundary.
(a)
(b)
Figure 4.7: (a) A convergence property of Gummel’s loop for the numerical solution of DD equations with and without including the trap models of grain boundary, and (b) A convergence behavior for the numerical solution of Poisson equation in the set of DD equations with and without
including the trap models of grain boundary, where VD = VG = 1.0 V .
50 Chapter 4 : Solution Techniques
4.4 : Illustration Examples 51
To explore the effect of grain boundary on the physical characteristics of simulated poly-Si TFT, we examine the computed electrostatic potential and electron density along the channel direction (x direction) shown in Figs. 4.8-4.9, respectively. The upper fig-ure of Fig. 4.8 shows the computed potential profile for the device under bias conditions VD = 0.5 V and VG = 0.5 V , and the lower one in Fig.4.8 is a cross-sectional view of the circled region in the upper figure. The upper figure of Fig. 4.9 shows the electron density and the lower one in Fig. 4.9 is a cross-sectional view of the circled region in the upper fig-ure. Along the channel region of the device, obviously, the simulated potential profile and electron density significantly reveal the effect of grain boundary on the computed physical quantities. As shown in Fig. 4.10, we compare the computed electrostatic potential with different trap models of grain boundary at VD = VG = 0.5 V . The case of DD simulation with the nonlinear trap model of grain boundary faithfully describes the traps effect on the charge distribution compared with DD simulation including only the linear trap model. The case of DD simulation without including any trap models does not reflect the effect of grain boundary on the computed potential.
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Figure 4.8: The upper figure is the simulated potential of the poly-Si TFT with VD = VG= 0.5 V . The lower one is a
cross-sectional view of the circled region in the upper figure.
4.4 : Illustration Examples 53
Figure 4.9: The upper figure is the simulated electron density of the poly-Si TFT with VD = VG = 0.5 V . The lower one is a cross-sectional view of the circled region in the upper figure.
54 Chapter 4 : Solution Techniques
Figure 4.10: Comparison of the computed electrostatic potential for the 2D DD simulation with three different trap models of grain boundary, where VD = VG = 0.5 V .