5.2 Simulation of 300 nm Poly-Si TFTs with Different Gate Structures
Two different TFT devices with 300 nm SG and GAA TFTs are investigated in this section.
GAA poly-Si TFT structure has been shown in Fig. 5.5(a). The used parameters of devices are shown in Table 5.1 [87]. Because the size of GB used is 300 nm, only one GB was assumed to exist in the channel and is perpendicular to the channel length. The position of GB was assumed to occur at three different locations, as depicted in Fig. 5.5(b). To explore the potential advantages of GAA poly-Si TFTs, we compare our calculated results with the data of SG poly-Si TFTs. The threshold voltage for these two devices is adjusted with varying channel doping and gate material. The extracted barrier height (EB) and the acceptor-liked trap surface density (NT A) at the grain boundary were used for GAA and SG structures. The doping concentration (NA) at the channel is calculated with [86]:
EB = q2NA 8ε (NT A
NA )2, (5.1)
where ε is the semiconductor permittivity. When EB is fixed, NAis proportional to (NT A)2. We decrease the concentration of the doping profile and increase the gate work function.
64 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
Table 5.1: The used parameters in the 3D device simulation of the 300 nm devices.
Device Parameter Setting value Device Parameter Setting value
Gate length 300 nm GB 15 nm
channel thickness 50 nm Work function 4.55 eV Channel width 300 nm Channel doping 1E16 Oxide thickness 15 nm LDD doping 2.5E18
LDD length 200 nm S/D doping 2.5E19
5.2 : Simulation of 300 nm Poly-Si TFTs with Different Gate Structures 65
Figure 5.5: (a) A schematic plot of the GAA poly-Si TFT. The device is with a square-shaped-surrounding gate. (b) Single grain boundary occurs at the position of A, B, and C.
66 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures ID-VGcharacteristics in GAA and SG without the grain boundary.
5.2 : Simulation of 300 nm Poly-Si TFTs with Different Gate Structures 67
Table 5.2: Effects of GB position on the device characteristics of the 300 nm GAA poly-Si TFT, where the size of single GB is 15 nm. Ionand Iof f are the on-state current and off-state current.
Symbol Vth Ion/Iof f DIBL(V) S.S(mv/dec)
w/o GB – 6e7 0.02 91
GB at A 4.56 5.7e7 0.042 105
GB at B 3.96 5.9e7 0.19 101
GB at C 5.45 5.6e7 0.24 107
Table 5.3: Effects of GB position on the device characteristics of the 300 nm SG poly-Si TFT, where the size of single GB is 15 nm.
Symbol Vth Ion/Iof f DIBL(V) S.S(mv/dec)
w/o GB – 2e7 0.04 101
GB at A 10.25 1.2e7 0.08 139
GB at B 7.02 1e7 0.06 134
GB at C 15.31 1.3e7 0.09 144
According to the definition in the chapter 2, we arrange the results in Tables 5.2 and 5.3.
68 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
Consequently, a reasonable of Vth = 0.62 V is obtained for both structures. Charac-teristics of ID-VD and ID-VG for devices without GB are firstly shown in Fig. 5.6. The off-state current, shown in Fig. 5.6(b), is suppressed with the 300 nm GAA poly-Si TFT by using a LDD doping profile close to the SG. The on-state current of the 300 nm GAA poly-Si TFT is about 3-times larger than that of the SG, so we expect that the 300 nm GAA poly-Si TFT can have a larger driving capability and yield a higher luminescence output.
Effect of single GB on parameters of the short channel effect for GAA and SG devices are then calculated and compared in Tables. 5.2 and 5.3, respectively. Vthis the normalized difference of threshold voltages for device with and without GB by the threshold voltage of the device without GB. Comparison shows that GAA poly-Si TFT exhibits good device characteristics compared with the results of SG one. It is observed that the worst case of Vthvariation on GAA could be reduced from 15% to 5.5% when GAA structure is consid-ered.
Vth versus the position of single GB, calculated with respect to different size of
sin-gle GB, is shown in Fig. 5.7. When the drain and source sides have GB, the variation of Vthbecomes significant. Vth can be reduced when the size of GB is decreased from 15 nm to 3 nm. Effect of GB is independent of the position when the size is relatively small compared with the channel length.
Normalized position of grain boundary
Figure 5.7: The effect of GB position on Vth variation of the 300 nm GAA poly-Si TFTs. Suppression of variation is observed when the size of GB is reduced from 15 nm to 0 nm (i.e., device w/o GB).
5.2 : Simulation of 300 nm Poly-Si TFTs with Different Gate Structures 69
70 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
5.3 Simulation of 90 nm Poly-Si TFTs including Quantum Mechanical Effects
We explore the effect of grain boundary (GB) position and size on electrical characteristics in 90 nm poly-Si thin film transistors (Poly-Si TFTs). To estimate the effect of GB, three-dimensional (3D) density-gradient- based drift-diffusion model is self-consistently solved with grain trap model for the square-shaped surrounding-gate (i.e., gate-all-around, GAA) poly-Si TFTs. The trap concentration and trap level are calibrated and extracted from the fabricated samples. Compared with device without GB, quantum mechanical simulation shows that the 90 nm GAA poly-Si exhibits significant threshold voltage variation ( 7.4%) when single GB locates at the drain side of device channel due to a largest shift of total inversion charge. The variation could be suppressed when the size of single GB is reduced.
For the same threshold voltage, the 90 nm GAA poly-Si TFT suffers more serious perfor-mance degradation than that of 300 nm device. It is mainly resulted from the short channel effect and quantum-confined GB trap near the drain side.
According to a scaling rule, the adopted parameters in our 3D simulation are shown in Tab. 5.4. We explore the intrinsic characteristics of the 90 nm GAA poly-Si TFT with and without GB appearing at C (i.e., the drain side) by using the quantum mechanical (i.e., the density-gradient based drift-diffusion model) and the classical transport (drift-diffusion
5.3 : Simulation of 90 nm Poly-Si TFTs including Quantum Mechanical Effects 71
model) simulations, shown in Fig. 5.8. The electron density distributions along the direc-tions of YY and ZZ are compared. Along different cutting lines, it is found that for the device without GB, the classical simulated electron density is higher than that of quantum mechanical result due to no dangling bonds and quantum confinement existing in channel region. For device with GB at C, both the classical and quantum mechanical simulations show the electron densities are reduced due to weakened gate controllability. It mainly results from a higher variation of the barrier height and then an enlarged effective oxide thickness. We note that the effect of single GB is significant in quantum mechanical sim-ulation (about 23% reduction), compared with the classical result (14% reduction). The reduction is the averaged relative error of the electron density with GB and without GB. If the size of GB increases, the effect of GB will result in larger reduction. The quantum me-chanical computed surface electrostatic potentials, shown in Fig. 5.9, are plotted along the channel direction from the source to drain sides with three different positions of GB. The size of GB is firstly fixed at the 4 nm. It is found that potential distributions are significantly affected by the position of GB compared with the result of device without GB. When GB appearing at C, a large variation of the barrier height (0.3 eV) occurs, shown in Fig. 5.9, which is substantially larger than that (0.2 eV) of classical simulation (not shown here) due to a quantum entanglement with grain trap concentration. If the position of GB could be controlled and locating near the neighborhood of B, the device has a lowest variation of the
72 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
Table 5.4: The used parameters in the 3D device simulation of the 90 nm devices.
Device Parameter Setting value Device Parameter Setting value
Gate length 90 nm GB 4 nm
channel thickness 10 nm Work function 4.55 eV Channel width 90 nm Channel doping 3.3e16 Oxide thickness 3 nm S/D doping 8.25e19
barrier height (it is about 0.04 eV) which means that the device has stable characteristics among the explored device with different positions of GB.
Distance along YY' (μm)
0.00 0.02 0.04 0.06 0.08 0.10
Electron density (x 1018 cm-3 )
0
0.000 0.003 0.006 0.009 0.012 Electron density (x 1018 cm-3 )
0
Figure 5.8: Along the (a) YY’ and (b) ZZ’ direction of the inset figures, the plots are the electron density without (w/o) and with (w/) GB when using quantum mechanical and classical models, where the gate voltage VG = 1.1 V.
5.3 : Simulation of 90 nm Poly-Si TFTs including Quantum Mechanical Effects 73
74 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
Along Source to Drain direction (nm)
Electrostatic potential (V)
Figure 5.9: The simulated electrostatic potential along the 90 nm device channel with respect to three different positions of GB. The case C (the grain boundary locates at the drain side) has a large peak and baffles the electron current.
5.3 : Simulation of 90 nm Poly-Si TFTs including Quantum Mechanical Effects 75
Table 5.5: The calculated variation of the total inversion charge of the 90 nm poly-Si TFT, where VG= 1.1 V and the size of GB = 4 nm. The A, B, and C are the same as shown in Fig. 5.5(b).
GB at A GB at B GB at C
ΔQinv 5.4% 3.3% 6.3%
The total inversion layer charge Qinvshown below is quantitatively calculated and com-pared among three positions of GB:
Qinv =
q· n(x, y, z)dxdydz, (5.2)
where the n is the quantum mechanical computed electron density per unit volume. Com-parison, shown in Tab. 5.5, is computed by estimating the variation of Qinv:
ΔQinv = Qinv|w/o− Qinv|w/
Qinv|w/o
. (5.3)
We find that the GB near the drain side has a large variation of the inversion charge under the on-state condition. The calculation confirms the argument discussed that GB locating at C significantly degrades the device performance including the degradation of the transport current and serious short channel effect. A comparison of the characteristics of ID-VD for the explored device under VG = 2 V are simulated when the size of GB is equal to the 4 v, shown in Fig. 5.10. It shows that the device with GB at C exhibits a largest reduction of the magnitude of the drain current. More than 2.5 times reduction is observed for the
76 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
device without GB and with GB at C. The further reduction of the drain current appears for the device with GB and A and C, compared with the device with GB at B and without GB, which confirms the examination in Tab. 5.5.
Effect of the GB’s size and position on the variation of threshold voltage of the 90 nm GAA poly-Si TFT is explored, shown in Fig. 5.11 The open-triangular shows the device without GB in the channel. When the drain and source sides have GB, a large variation of the threshold voltage is introduced. For the device with GB locating at B, the variation of the threshold voltage is less dependent on the grain trap. The variation of the threshold voltage could be suppressed when the size of GB is reduced from the 6 nm to 2 nm. Effect of GB is independent to the position of GB when the size of GB is relatively small enough.
With an increasing of the size of GB, the variation of the threshold increases and then the current decreases.
We further explore the short channel effect including the drain induced barrier lowering (DIBL), the subthreshold swing (S.S.), and the ratio of the on-state and the off-state currents between the 90 nm and 300 nm GAA poly-Si TFTs. The DIBL and the S.S. are computed by:
S.S.= ∂(log10ID)
∂VG |VD=0.25V, (5.4)
DIBL= Vth|VD=0.25V − Vth|VD=1.1V. (5.5)
Compared with the 300 nm GAA poly-Si TFT, the 90 nm device shows serious performance
5.3 : Simulation of 90 nm Poly-Si TFTs including Quantum Mechanical Effects 77
degradation that introduced from the effects of GB and quantum confinement, shown in Tabs. 5.7 and 5.6.
In this work, we have studied the dependence of electrical characteristics on the po-sition and size of single GB in the 90 nm poly-Si TFT. The effect of GB in sub-100 nm square-shaped surrounding-gate poly-Si TFTs have been studied by solving the 3D quan-tum correction transport model. The position and size of single GB significantly affect the intrinsic performance of the 90 nm GAA poly-Si TFT. The GAA poly-Si TFTs suffer se-rious short channel effect and performance degradation when the device channel is scaled into the sub-100 nm. The device’s GB locating at the drain side will result in large charac-teristic variation. To reduce the short channel effect, the size of GB should be accordingly reduced with the reduction of channel length in the nanoscale GAA poly-Si TFTs era. We are currently exploring the effect of GB in TFT-LCD display using ultra-small poly-Si TFTs.
78 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
VD (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
I D (A)
0.0 4.0e-5 8.0e-5 1.2e-4 1.6e-4
w/o GB
w/ GB at B
w/ GB at A w/ GB at C
Figure 5.10: A comparison of the computed ID-VD for the device with different positions of GB, where the size of GB = 4 nm and VG= 2 V. More than 2.5 times difference is observed between the 90 nm poly-Si TFT w/o GB and the device w/
GB at C.
5.3 : Simulation of 90 nm Poly-Si TFTs including Quantum Mechanical Effects 79
Normalized position of grain boundary
0.0 0.2 0.4 0.6 0.8 1.0
Figure 5.11: The effect of the position of GB on the variation of threshold voltage for the 90 nm GAA poly-Si TFT. The open-triangular is the device without GB in the channel.
The variation is suppressed when the size of GB is reduced from the 6 nm to 2 nm.
80 Chapter 5 : Characteristic Simulation of Poly-Si TFTs with Different Gate Structures
Table 5.6: The computed short channel effect of the 300 nm GAA poly-Si with different positions of GB.
Symbol Vth Ion/Iof f DIBL(V) S.S(mv/dec)
w/o GB – 6e7 0.02 91
GB at A 4.56 5.7e7 0.042 105
GB at B 3.96 5.9e7 0.19 101
GB at C 5.45 5.6e7 0.24 107
Table 5.7: The computed short channel effect of the 90 nm GAA poly-Si with different positions of GB.
Symbol Vth Ion/Iof f DIBL(V) S.S(mv/dec)
w/o GB – 9e7 0.04 101
GB at A 7.2 6.4e7 0.07 120
GB at B 4.75 6.8e7 0.06 113
GB at C 7.4 6.1e7 0.09 123
Chapter 6
Performance of Poly-Si TFT Circuit Drivers
T
he chapter investigated the methods for the driving circuit and covers the organic light emitting diode(OLED). OLED display has several advantages over TFT-LCDs and penetrate into various applications. Because of the effects of GB, it is hard to simulate the active-matrix circuit. We develop the mixed-mode method.In the mixed-mode simulation, the solution of the basic transport equations for the semi-conductor devices is directly embedded into the solution procedure for the circuit equations.
Compact modelling is thus avoided and much higher accuracy is obtained.
81
82 Chapter 6 : Performance of Poly-Si TFT Circuit Drivers
6.1 The Explored Poly-Si TFT Circuit
Currently, well-established SPICE model of GAA poly-Si TFTs is not available for cir-cuit simulation. We develop a circir-cuit-device coupled mixed mode simulation technique to explore the circuit behavior. The mixed mode methods contains devices and circuits simu-lation.
We also employ a numerical simulation to explore the OLED devices. The numerical simulation of the continuity and Poisson equations has been carefully extended to treat the interfaces of multi-layer organic structure.The experimental structure is shown in Fig. 6.1 which implies that a simulation is necessary. One OLED device is equal to one poly-Si TFT coupling one capacitance. From the results shown in the figures 6.2-6.3 exhibit the comparison results for our model with the measured OLED data with red, green, and blue color, respectively. Our simulation presents good accuracy when describing the OLED physical characteristics in both the cut-in and the on-state regions. We also compare our OLED simulation with others [26], shown in Fig. 6.3. This OLED device is used in my thesis. After the discussion of OLED, we show the simulation of our circuit in Fig. 6.1.
The mixed mode source codes is listed in appendix B. A flow chart of OLED’s extracting method is shown in Fig. 6.4, and the extracting parameters of OLED are shown in Tab.
6.1. In the beginning, the work function and doping profile of channel should be tuned.
Calibrating with measurement data, we can get a suitable value of threshold voltage. After
6.1 : The Explored Poly-Si TFT Circuit 83
this step, We must tune the value of capacitor because it decides on-state current. If the target of threshold voltage and on-state current are correct, the extracting steps will finish.
84 Chapter 6 : Performance of Poly-Si TFT Circuit Drivers
Figure 6.1: (a) A diagram of the multi-layers OLED structure (b) and 2T1C active-matrix driving circuit and the OLED compact circuit.
6.1 : The Explored Poly-Si TFT Circuit 85
Figure 6.2: Comparison of I-V between measured (symbol curve) and simulated (solid curve) OLED device, where (a) is the red light (b) and is the green light.
86 Chapter 6 : Performance of Poly-Si TFT Circuit Drivers
Figure 6.3: Comparison of I-V between measured (symbol curve) and simulated (solid curve) OLED device, where (a) is the blue light (b) and is our adopted OLED device.
6.1 : The Explored Poly-Si TFT Circuit 87
Start
Tune the doping profile of channel and the gate work
function
Calibrate the threshold voltage
Tune the capacitance
Does the on-state current meet the
target ?
Finish
No Yes
Yes No
Figure 6.4: A flow chart of OLED’s parameters extraction by using device simulation.
88 Chapter 6 : Performance of Poly-Si TFT Circuit Drivers
Table 6.1: The extracted parameters of OLED.
OLED type Red Green Blue adopted OLED
Capacitor 40 fF 35 fF 36 fF 30 fF
Work function 4.4 eV 4.45 eV 4.45 eV 4.55 eV Channel doping 1.6E16 cm−3 2E16 cm−3 2E16 cm−3 1E17 cm−3
6.2 : The Mixed Mode Equations of the Poly-Si TFT Circuit 89
6.2 The Mixed Mode Equations of the Poly-Si TFT Cir-cuit
The mixed-mode methods contains devices and circuits simulation. Eq. 6.1 - 6.12 are subjects to proper initial and boundary conditions with respect to the node voltage, loop current potential (φ) , electron density (n), and hole density (p).
Δφ = q Above three equations are about device simulations. From Fig. 6.1(b), we can write circuit equations:
90 Chapter 6 : Performance of Poly-Si TFT Circuit Drivers
6.3 Results of the Circuit Simulation
Clearly, the left inset shows that the delay time of GAA circuit is about 0.12 μs which is only one ninth of SG circuit. This property may benefit the application of high-resolution display panel. Usually GB appearing on the drain side is the worst situation for devices, where GAA circuit still has an effect to yield higher driving current than that of SG one without GB. 2T1C circuit with GAA poly-Si TFTs can sustain stable currents. We believe similar results can occur for more complicated active matrix circuit, such 4T2C circuit using GAA poly-Si TFTs. Fig. 6.6 shows variation of VOLED with respect to Vth. High channel doping not only increases Vthbut also trap concentration of single GB. The latter one results in a serious variation of VOLED for SG circuit. GAA circuit yields more stable driving capability. Finally, we will discuss the device of T2. The node of VOLED is quite sensitive to the current, moreover, it is mutual influential to Vgs. If we can set Vgs to a specific constant, we can improve the variation of VOLED. To change T2to a p-type poly-Si TFTs is a possible way to make Vgs to a given constant because the source becomes the bias of VDD. The degradation of VOLED can be improved efficiently.
Figure 6.5: The circuit behavior of a 2T1C active matrix driver. As shown in the Fig. 6.1 (b), T1 is for switching and T2 is for driving. The GAA circuit exhibits short delay time and stable current.
Figure 6.6: The variation of VOLED versus Vth. A higher Vth implies a serious variation of OLED voltage due to heavy channel doping.
6.3 : Results of the Circuit Simulation 93
Figure 6.7: Equivalent circuit and driving signals of Goh’s proposed pixel circuit. (1) Initialization period, (2) compensation period, (3) and data-input period
Goh proposed a new TFT pixel circuit for active-matrix organic light-emitting diode
Goh proposed a new TFT pixel circuit for active-matrix organic light-emitting diode