In order to evaluate the performance of our method, we examine these methods mentioned above based on Texas Instruments TMS320C55x family of signal processors. In table 3[34], we show the features of TMS320C55x. In addition, we assume the calculated CPU clock cycles of the realization of the RSA decryption with the following parameters as Table 4. The CPU clock cycles needed for processing the original RSA decryption method, decryption method based on the CRT, and our proposed method are given in Table 5, Table 6, and Table 7. The critical factor in influencing the speed of RAS decryption is the computation of modular multiplication. We apply the square and multiply algorithm to compute the modular exponentiation [27]. The square and multiply algorithm needs 3n/2 modular multiplications for an n-bit exponent. The original RSA decryption method needs modular multiplication only one time. The decryption method based on the CRT needs modular-multiplication two times. Because there is a difference in the length of d and n in modular multiplication, the clock cycles needed by the decryption method based on the CRT are less and the speed of this method is faster than the speed of the original decryption method.
However, as our proposed method needs modular multiplication four times and the length of d and n is much shorter, the clock cycles needed are much less and the speed is much faster.
As demonstrated in Table 6, due to the characteristics of chip TMS320C55x, the clock cycles needed by original decryption method is more than the clock cycles assessed in chapter four. Nevertheless, the
Table 3 The Features of TMS320C55x [32]
High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor (DSP)
– 6.25-/5-ns Instruction Cycle Time – 160-/200-MHz Clock Rate
– One/Two Instructions Executed per Cycle – Dual Multipliers (Up to 400 Million
Multiply-Accumulates Per Second (MMACS)) – Two Arithmetic/Logic Units
– One Internal Program Bus
– Three Internal Data/Operand Read Buses – Two Internal Data/Operand Write Buses
Instruction Cache 24K Bytes
160K x 16-Bit On-Chip RAM – Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
– 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM)(256K Bytes)
16K × 16-Bit On-Chip ROM 32K Bytes 8M × 16-Bit Maximum Addressable External
Memory Space
32-Bit External Memory Interface (EMIF) – Asynchronous Static RAM (SRAM) – Asynchronous EPROM
– Synchronous DRAM (SDRAM) – Synchronous Burst SRAM (SBSRAM)
On-Chip Peripherals – Two 20-Bit Timers
– Six-Channel Direct Memory Access(DMA) Controller
– Three Multichannel Buffered Serial Ports (McBSPs)
– 16-Bit Parallel Enhanced Host-Port Interface (EHPI)
– Programmable Digital Phase-Locked Loop (DPLL) Clock Generator
– Eight General-Purpose I/O (GPIO) Pinsand Dedicated General-Purpose Output (XF) On-Chip Scan-Based Emulation Logic
IEEE Std 1149.1 (JTAG) Boundary ScanLogic 3.3-V I/O Supply Voltage
1.6-V Core Supply Voltage
Table 4 Parameters of The RSA Decryption
RSA modulus n 2048bits 1024bits 512bits RSA exponent length 2048bits 1024bits 512bits
message length 2048bits 1024bits 512bits level-1 prime length 1024bits 512bits 256bits level-2 prime length 512bits 256bits 128bits Table 5 Numbers of CPU Clock Cycles for Realization RSA Decryption
between Three Methods (Key Length = 2048 bits)
Clock Cycles Computational Cost Original Decryption
Method 269083092 100%
Decryption Method
Based on CRT 55491364 20.62%
New Decryption
Method 30634747 11.37%
Table 6 Numbers of CPU Clock Cycles for Realization RSA Decryption between Three Methods (Key Length = 1024 bits)
Clock Cycles Computational Cost Original Decryption
Method 35635338 100%
Decryption Method
Based on CRT 9985827 28.02%
New Decryption
Method 5506659 15.45%
Table 7 Numbers of CPU Clock Cycles for Realization RSA Decryption between Three Methods (Key Length = 512 bits)
Clock Cycles Computational Cost Original Decryption
Method 5145156 100%
Decryption Method
Based on CRT 1633335 31.75%
New Decryption
Method 897929 17.45%
computational cost needed by each kind of decryption method is almost the same with the computational cost that we assessed before. Comparing the results in Table 5, Table 6, and Table 7, we find that, with the increase of key length, the computational costs which can be saved by decryption method based on the CRT and by our new decryption method also increase. Let’s take another example. In table 7, when the key length is 2048bits, the decryption method based on the CRT only needs 20% of the computational cost of original decryption method. Furthermore, our new decryption method only needs 11% of the computational cost of original decryption method.
The memory spaces needed for processing the original RSA decryption method, decryption method based on the CRT, and our proposed method are given in Table 8, Table 9, and Table 10. As demonstrated in Table 8, Table 9, and Table 10, our new decryption method and decryption method based on the CRT need more memory space respectively than original decryption method does. When key length is 1024bits, the memory space needed by decryption method based
Table 8 The Memory Spaces for Realization RSA Decryption between Three Methods (Key Length = 2048 bits)
Memory Space Increase Percentage Original Decryption
Method 11347bytes 100%
Decryption Method
Based on CRT 12440bytes 109.63%
New Decryption
Method 14704bytes 129.58%
Table 9 The Memory Spaces for Realization RSA Decryption between Three Methods (Key Length = 1024 bits)
Memory Space Increase Percentage Original Decryption
Method 6611bytes 100%
Decryption Method
Based on CRT 7558bytes 114.23%
New Decryption
Method 8985bytes 135.91%
Table 10 The Memory Spaces for Realization RSA Decryption between Three Methods (Key Length = 512 bits)
Memory Space Increase Percentage Original Decryption
Method 4243bytes 100%
Decryption Method
Based on CRT 5048bytes 118.97%
New Decryption
Method 6005bytes 141.53%
on the CRT is 14% more than the memory space needed by the original decryption method. The memory space needed by our proposed method is 36% more than the memory space needed by the original decryption method. Comparing the results in Table 8, Table 9, and Table 10, we find that, with the increase of key length, the memory space increased by decryption method based on the CRT and by our new decryption method is lessening respectively. For example, in Table 8, when key length is 2048bits, the memory space of decryption method based on the CRT increases 10% and the memory space of our proposed method only increases 30%.
As demonstrated by the results of implementation, when little amount of memory space is increased, the speed of RSA decryption operation can be greatly accelerated. Furthermore, when the key length is increased, the memory space needed to increase is reducing, but the speed of RSA decryption operation can be accelerated much significantly.
Therefore, as it can be seen from the results of implementation, our new decryption method is more efficient than other two kinds of decryption method.