CHAPTER 2 OSCILLATOR THEORY
2.8 Inductor
In integrated RF works in silicon, inductors are normally implemented as a planar spiral-shaped metal. Figure 2.17 shows the top view of an example spiral inductor in silicon, realized using the top metal layer while the metal layer below the top metal layer is used for an interconnection for terminal 2. Figure 2.18 shows an equivalent electrical circuit model for the spiral inductor, obtained using an electromagnetic simulation. In this model, L, Rs, Rp, and Cp represent inductance, metal loss due to the skin effect, substrate loss, and metal-substrate capacitance, respectively. Cs accounts for the metal overlap capacitance between the top metal and the metal below. Using Cadence, measures the quality factor, Q of the spiral inductor (See the note below) over the frequency range.
Figure 2.18 Spiral inductor equivalent electrical circuit model
is discussed in class, the quality factor, Q is originally defined for a
“ resonator ＂ as：
where is the resonance frequency. For a given resonator whose resonance frequency is fixed, Q is not a function of frequency. Since inductors are not resonators, the original Q definition above cannot be used for inductors. However, the following frequency -dependent Q definition may be used instead as the quality factor for inductors:
It can be easily shown that Q (ω) in (2.16) is on the same order as, but not exactly the same as,
where Z (ω) is the frequency-dependent input impedance of a given inductor. RF engineers traditionally choose to use (2.15) over (2.16) due to the simplicity of (2.17). In
the problem above, we can evaluate the Q of the spiral inductor using (2.17) while the input impedance Z (ω) shown in Figure 2.18 can be measured using Cadence.
CHAPTER 3
LC TANK OSCILLATOR THEORY
3.1 LC tank oscillator architecture
Figure 3.1 (a) Ideal, (b) realistic LC tank
As shown in Figure 3.1(a), an inductor L1 placed in parallel with a capacitor C1 resonates
at a frequency . We say the circuit has an infinite quality factor, Q. In practice, inductors (and capacitors) suffer from resistive components. When a charged capacitor is connected to an inductor, the conventional analysis is to equate the voltage across the capacitor with the voltage across the inductor.
(3.1) Differentiating, we get
(3.2) This is then recognised as having as a solution of simple harmonic motion (SHM),
(3.3) The traditional analysis assumes that when current is switched into the inductor, it appears instantaneously at all points in the inductor; the use of the single, lumped quantity L implies this. Similarly, it is assumed that the electric charge density at all points in the capacitor is the same; that there are no transient effects such that the charge density is greater in certain regions of the capacitor plates.
For this circuit reader can show that the equivalent impedance is given by
(3.4)
(3.5) that is, the impendence does not go to infinite at any s=jω. We say the circuit has a finite
Q. The magnitude of Zeq in (3.5) reaches a peak in the vicinity of , but the actual resonance frequency has some dependency on Rs.
Let us now consider the “tuned＂ stage of Figure 3.2(a), where an LC tank operatesas
the load. At resonance, and the voltage gain equal (Note that the gain of the circuit is very small at frequencies near zero). Also from Figure 3.2(b), the frequency dependent phase shift of the tank never reaches .Thus, the circuit does not oscillate.
Figure 3.3 Output signal levels in a tuned stage
Before modifying the circuit for oscillatory behavior, let us observe another interesting property of the gain stage of Figure 3.2 (a) that distinguishes it from a common-source topology using a resistive load. Suppose, as shown in Figure 4.3, the stage is biased at a drain current. If the series resistance of Lp is small, the dc level of Vout is close to Vdd.
We expect Vout to be an inverted sinusoid with an average value near Vdd because the inductor cannot sustain a large dc drop. In other average value of Vout deviates significantly fromVdd, then the inductor series resistance must carry an average current greater than I1. Thus, the peak output level in fact exceeds the supply voltage, an import and often useful attribute of the LC load. For example, with proper design, the output peak-to-peak swing can be large than Vdd.
3.2 LC cross coupled oscillator theory
Calculating the impedance seen at the collector of Q1 and Q2 as shown in Figure 3.4(a),
we note that positive feedback yields (shown in Figure 3.4 (b) and Equations 3.6-3.10). Thus, if |Rin| is larger than or equal to the equivalent parallel resistance of the tank, the circuit oscillates. This topology is called a negative-Gm oscillator.
Figure 3.4 (a) Circuit to calculate the input impedance of cross coupled pair, (b) equivalent circuit of cross coupled pair
(3.6) (3.7) (3.8)
(3.9)
(3.10)
Figure 3.5 LC cross coupled VCO
3.3 Dual-band LC VCO
3.3.1 Conventional Dual-band LC VCO
Basically the circuit is derived using two similar half circuits as that shown in Figure 3.6 The circuit is formed by a pair of nMOS (MN1 and MN2) transistors and pMOS (MP1 and MP2) transistors which are cross coupled to create positive feedback loops in parallel with LC (L1, L2, L3 and L4) resonators. The capacitors C are implemented by the diode varactors JV1, JV2, JV3 and JV4 to control the resonant frequency of the LC tanks. The two half circuits share the same dc current, so that they have two frequency outputs and only one dc power dissipation, leading to saving the power. The Cp is used to decouple the ac signals from the upper and lower half circuits. The circuit uses single VDD and GND that produce dual-band frequencies at the same time. However, the design of dual-band VCO＇s presents a considerable challenge because of the simultaneous requirements for wide frequency range, lower current consumption and low power consumption.
3.3.2 Switched Resonators
A possible way to achieve a wide tuning range is to use a switched capacitor bank in a resonator. To qualitatively discuss the need for a switched resonator over a switched capacitor bank, consider the – VCO shown in Fig.3.7
Figure 3.7 Schematic of a dual-band VCO.
Fig. 3.8(a) and (b) shows switched resonators including mutual inductance (M). The inductance seen between ports 1 and 2 are changed by turning the switch transistor on and off. The equivalent circuit of the switched resonator is shown in Fig. 3.8(c). In the case that port 2 is grounded and that and have no mutual effect (M=0), the resonator is simplified into the circuit in Fig. 2(d) when the switch is on, and into the circuit in Fig.
2(e) when off. When the switch is off, the inductance of switched resonator is largely determined by the two inductors while the capacitance is determinedbythe parasitic capacitances ( and ) of the inductors and the capacitances ( and ) at the drainoftheswitchtransistor.Theextractedinductanceusingmeasurements and the simple inductor model is lower due to the effects of in series with , and of the switch transistor (M4 ). When the switch is on, the channel resistance is close to zero.Theinductance and capacitance of the switched resonator are switched by shorting out L2, the capacitances associated with L2,L1,and the switch transistor.The
inductance is approximately L1 and the capacitance is Cp1, thus, leading to simultaneous decreasesof inductance and capacitance.
Figure 3.8 (a) and (b) Two-use configurations of a switched resonator.
3.3.3 Switched Inductance
Switched resonators circuit compare to conventional dual band VCO circuit, less power consumption and smaller die area. But switched resonators circuit still needs two inductor, so I have a new idea to use an inductor achieving two inductance.(Figure3.9)
Switch Metal6(2finger)
Metal5(4finger)
Figure 3.9Switched Inductance diagram
When switch off, the inductance seems to Tsmc 0.18um four fingers spiral inductor.
When switch on, the inductance seems to Tsmc 0.18um two fingers spiral inductor.
But when switch on (two fingers), we must think about the MOS parasitic resistance the mutual inductance between inner circle and outer circle. So my method is using RF model from Tsmc to import Ansoft Designer and run EM analysis. But we still consider MOS switch parasitic capacity and resistance. RF MOS model is as Figure3.10.
Rg
So MOS main parasitic capacity is approach (C1//C3)+C2.And MOS main parasitic resistance is approach Rd+Rs
If we decide MOS size, then we can estimate C1,C2,C3,Rd,Rs value approximately. So we include these informations in our circuit design. My circuit is a conventional cross-couple type(Figue3.11) to generate negative resistance to cancel resistance because of LC tank unlimited Q value.
R1
First we want varactor C2 to have maximum variable capacitance. Because we must control C2 both sides voltage to make sure capacitance, then we add C1 so C2 both sides voltage doesn’t change with oscillator. If we want C2 to dominate capacitance, the C1 capacitance must be biggest as we can accept.R1, R2 also must be large enough so it seems AC open. We use a NMOS and give voltage from it’s gate to make a current source and control current. Output buffer exist for signal isolation between LC tank and measure instrument.
Signal in
Signal out
Figure 3.11 Output buffer
We adopted a fixed current source and common-drain architecture. A fixed current source can avoid that output buffer current changes with signal in. If the output buffer current changes with signal in, the signal out power can’t export stably.
CHAPTER 4
Figure 4.1 Switch off (4 finger inductance) phase noise
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 4.2 Switch off (4 finger inductance) tuning range freq. tuning range2.2GHz~2.45GHz
m1noisefreq= Figure 4.3 Switch on (2 finger inductance) phase noise
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 4.4 Switch on (2 finger inductance) tuning range freq. tuning range4.8GHz~6GHz
output buffer swing=0.4V
total power(include output buffer)=3.8mA*1.8V
4.2 Measurement
Figure 4.5 Switch off (4 finger inductance) phase noise
Figure 4.6 Switch off (4 finger inductance) tuning range
Figure 4.7 Switch on (2 finger inductance) phase noise
Figure 4.8 Switch on (2 finger inductance) tuning range freq. tuning range4.2GHz~5.4GHz
output buffer swing=0.38V
total power(include output buffer)=4.2mA*1.8V
Figure 4.9 Layout
CHAPTER 5
VCO DESIGN FLOW
5.1 Design procedure
The simulation software Spectre RF is used to design analogy circuit. After the layout of the circuit is finished, the LPE (layout parameter extraction) is done to extract parasitic components which is put into the circuit and we simulated complete circuit again.
System Spec
5.2 Test procedure
Measurement of output spectrum and output power performances were obtained using an Adventest R3162 spectrum analyzer.
Power Supply
Ammeter
Die under PCB broad Spectrum Analyzer
Figure 5.2 Experimental set-up
On-board measurements of output spectrum and output power performances were obtained using an Adventest R3162 spectrum analyzer.
CHAPTER 6 CONCLUSION
In first band (switched off,2.2~2.45G),simulation meets measurement mostly, but in measurement spectrum signal isn’t pure. Because my PCB board transmission line width is matching for 5GHz (26mil in 5GHz, S11=-28dB), so spectrum in 5GHz is much pure than 2GHz (26mil in 2GHz, S11=-13dB). Spectrum in 5GHz, we can see the appearance of tuning range shift. Because we ignore inductor’s outside metal of the inner circle when switch on. This also has inductance and generates mutual inductance with inner circle. So these reason made real inductance over exception.
And switch’s parasitic also effects Q value of inductor, so phase noise in measurement is higher than simulation.
Compare with report before[20]
Parameter Dual band
-125dBc/MHz -123dBc/MHz -118dBc/MHz -106.3dBc/MHz
Die
Size(mm^2)
1.3x0.69 1.3x0.69 1.38x0.77 1.38x0.77
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Vita and Publication
姓 名: 楊岱原
出生日期: 中華民國七十年八月十四日 學經歷:
國立成功高級中學 (86 年9 月~89 年6 月)
國立交通大學電子工程學系 (89 年9 月~94 年6 月) 國立交通大學電子研究所碩士班 (94 年9 月~96 年7 月)
發表著作:
1. H. L. Kao, D. Y. Yang, Albert Chin, and S. P. McAlister, “2.4/5 GHz Dual-Band LC VCO using Variable Inductor and Switched Resonator,” IEEE MTT-S Int’l Microwave Symp. Dig., pp., June 12-17, 2007.