1.1 Overview of Poly-Si Thin-Film Transistor (Poly-Si TFT)
Since the first Polycrystalline-Silicon Thin Film Transistor (Poly-Si TFT) was published by C.H.Fa et al.[1] in 1966, it attracted most of the scientists who work in the Panel Display. Therefore, many researches devoted themselves on how to improve the performance of TFT has been started at that time. TFTs also play lots of roles in the panel industry, like Active Matrix Liquid Crystal Display (AMLCD)[2, 3], Static Random Access Memory (SRAMs)[4, 5], Electrical Erasable Programming Read Only Memories (EEPROM)[6, 7], etc. And among theses applications, the application of active matrix liquid crystal display was the major driving force to promote the developments of Poly-Si TFTs technology.
For the skills in the prior art in TFTs, it is well know that amorphous silicon had been a popular material to be used to fabricated on TFTs in AMLCD, due to its compatibility with low processing temperature on large-area glass substrate. However, there existed a disadvantage with its low electron mobility (<1 cm2/Vs), which hard to realize the integration of the switching pixels with the peripheral driver circuit on the same substrate to further reduce the prime cost. Recently, one solution have developed to over come the tough problem above described is to use polycrystalline silicon to be use as the channel film, due to its electron mobility higher than amorphous silicon. On the other hand, poly-Si TFTs plate also have higher panel resolution than amorphous-Si one, because it has larger aperture ratio in each pixel. Thus, how to improve the performance of poly-Si TFTs is the most important issue so as to realize the concept of System-On-Panel (SOP) [8].
With equal requirement of electrical characteristic to MOSFETs, TFTs also work hard to achieve high driving current, low leakage current, low threshold voltage and low sub-threshold swing.
To improve leakage current, there exist two ways to approach. First of all, we need to know various leakage mechanisms, like space-charge limited flow of hole from source to drain, thermal emission of carriers via grain boundary traps in the depletion regions, parasitic bipolar effect, impact ionization in the drain depletion region, band-to-band tunneling in the depletion region, and field emission via grain boundary traps[9]. Therefore, one of the problems is the large electric field across gate dielectric between gate and drain electrode when biasing gate voltage at leakage current region, and the other one is lots amount of defect states in grain boundary in the drain side junction.
Several novel device structures have been reported to reduce the leakage current with the approach of reduce the electric field between gate and drain electrode. Past lectures show these technologies that including Lightly Doped Drain (LDD) structure[10-12], source overlap and drain offset structure[13-15], Field Induce Drain (FID) structure[16], N-P-N gate structure[17], Floating Sub-Gate Structure with using photoresist reflow[18, 19], Air Cavity structure[20], High-k Spacer Offset-Gated structure[21], Vertical Bottom-Gate Structure[22], Gate Overlapped LDD (GOLDD) structure[23-25], Amorphous Silicon Buffer structure[26, 27], and T-gate Technology[28].
Except for using new structures, reducing defect states in grain boundary is also an important method. As we know, defect states in the grain boundary or in the interface between gate dielectric and channel serve as the trapping centers. Since free carrier be trapped in the trap sites, they will not contribute to the conduction current
to reduce the defects and defects related grain boundary, some effective treatment methods have been reported to enlarge grain size and passivate the defects. First, amorphous-silicon can be crystallizes to polycrystalline silicon typically via SPC(solid phase crystallization)[29], ELA( excimer laser annealing)[30, 31] and MILC(metal-induce lateral crystallization) [32]. Each of above method has its advantages and disadvantages. Besides, in order to passivate the defect states, introducing ions to bonding with defects have several technologies been reported, that including plasma treatment[33-40], solid phase diffusion[41], and ionic implantation[42-47], etc. As the trapping centers decrease, it will also help to increase the efficiency of free carriers contributed conducting current.
1.2 Recent High-k Dielectric
Furthermore, to improve the driving current and to have better sub-threshold swing, high-k gate dielectric is one of the solutions. There are many kinds of the candidate materials to alter the SiO2, due to the trend of scaling down length of device, which accompany with thinner dielectric thickness. High-k insulator can be deposited physically thicker for the same equivalent electrical oxide thickness (EOT), thus offering significant gate leakage current reduction, as demonstrate by several groups [48].
In the past studies, several new high-k gate dielectric materials, like Al2O3 and Ta2O5, were suggested to increase gate capacitance density so as to improve the mobile carrier density in the channel region. However, the k value of Al2O3 is 9~10 and is not high enough, and the improvement of the device performance is not apparent[49]. On the other hand, it is necessary to use a thick Ta2O5 as the gate dielectric in TFTs to reduce the gate leakage current, due to its narrow band-gap[50] .
Consequently, Hafnium-oxide based materials, such as HfO2, HfSixOy, HfOxNy and HfSixOyNz, have been provided with some better characteristics, that including high-permittivity, wider band-gap, and superior thermodynamic stability on silicon[48]. Recent researches show that only replacing gate insulator may not sufficient for device scaling, because poly-depletion effect can not be ignore for the sub-2-nm evolution any more. Besides, temperature for the dopant activation in the poly-Si gate electrode is always higher than the melting point of the glass substrates, which is not suitable for the applications of panel industry. By the way, metal gate does not need dopant activation process, and therefore to combine metal gate with HfO2 will have the greatest potential for the future CMOS technology[48].
These years, some reports had showed that high-k insulator used on poly-Si TFTs.
Not only for using in peripheral integral circuits TFTs[51], but also using in the (Silicon-Oxide-Nitride-Oxide-Silicon) SONOS-Type memory of TFTs[52, 53]. As long as TFTs combine with high-k dielectric, some excellent device performances can be achieved, that including high driving current, low threshold voltage, and low sub-threshold swing.
1.3 Review of Introduce Fluorine and Nitrogen
For reducing trap states in the grain boundary or in the interface, plasma treatments could easily introduce some species, like hydrogen[36], oxygen[33, 34], deuterium[35] by gas H2, D2, O2. And solid phase diffusion methods also reported to introduce fluorine into poly-Si by thermal diffusion[41]. For the past reports, fluorine and nitrogen have better performances than hydrogen, and states passivated by hydrogen could easily dehydrogenate undergo an Aluminum alloy process.
Since fluorine introduces into poly-Si can achieve higher driving current, lower
54], it can help to realize the ideal of transfer characteristic of TFTs. On the other hand, fluorine also passivate the deep states in the band gap of poly-Si[47], which lead to enhance better reliability. And nitrogen also has its superiority in performance and reliability in TFTs[37-40, 42, 43].
1.4 Motivation
To conclude and combine the advantage above described, we seek for poly-Si TFTs with excellent performances with lower leakage current, higher driving current, lower threshold voltage, and lower sub-threshold swing. Therefore, we take fluorine or nitrogen and high-k insulator together into TFTs processes. And for the limited of melting point of glass substrates, we need low temperature processes to be processed.
Gate last process would become our choice, and detail will be discussed in the chapter 2.
In addition, long-term reliability issues are always what we concerned in Thin Film Transistor. We use the methods of Positive Bias Temperature Instability (PBTI) and Hot Carrier Stress (HCS) stressing our device. The PBTI issue earlier major appears in n-channel device due to the “ high ” state in the inverter operation in CMOS circuit. To date, PBTI also play an important role in the TFTs in the panel, which used in switching elements or in the integral circuits. To deserve to be mentioned here, we also have the same reliability problems with high-k dielectric.
There will have more completed situations to be discussed in this thesis.
1.5 Organization of Thesis
In this section, I will show our research efforts. This thesis is organized as follow:
introduces fluorine and nitrogen, and finally motivation are described in this section.
In chapter 2, experimental process flows, and electrical parameter extraction are shown.
In chapter 3, the best implant conditions of fluorine and nitrogen within our experiments were determined.
In chapter 4, since the best fluorine implant condition will be use to compare with control sample which does not introduce fluorine. To qualify how the fluorine can strength the reliability, Hot Carrier Stress and Positive Bias Temperature Instability would be use to be our methods. For the later half of this chapter, the same methods will be to play into practice in nitrogen.
In chapter 5, at the end of this thesis, we will make conclusions and future works.