[3-1] W. C. Chen, H. C. Lin, Y. C. Chang, C. D. Lin, and T. Y. Huang, “In situ doped source drain for performance enhancement of double-gated poly-Si nanowire transistors,” IEEE Trans. Electron Devices, Vol. 57, No.7, pp.
1608-1615, Jul. 2010.
[3-2] E. R. Hsieh and S. S. Chung, “A new type of inverter with junctionless (J-Less)
- 42 -
transistors,” Silicon Nanoelectronics Workshop (SNW), pp. 1-2, 2010.
[3-3] M. Masahara, K. Endo, Y. Liu, T. Matsukawa, S. O’uchi, K. Ishii, E. Sugimata, and E. Suzuki, “Demonstration and analysis of accumulation-mode double-gate metal-oxide-semiconductor field-effect transistor,” Jpn. J. Appl.
Phys, Vol. 45, No. 4B, pp. 3079-3083, Apr. 2006.
[3-4] P. Ratnam and A. B. Bhattacharwa, “Accumulation-punchthrough mode of operation of buried-channel MOSFET's,” IEEE Electron Device Lett., Vol. 3, No. 7, pp. 203-204, Jul. 1982.
[3-5] M. R. Wordeman, “Characterization of depletion mode MOSFET's,” IEDM Tech. Dig., pp.26-29, 1979.
[3-6] T. Y. Chan, J. Chen, P. K. Ko and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” IEDM Tech. Dig., pp.718-721, 1987.
[3-7] C. W. Lee, D. Lederer, A. Afzalian, R. Yan, N. Dehdashti, W. Xiong, and J. P.
Colinge, “Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs,” Solid-State Electronics, Vol. 52, No. 11, pp.
1815-1820, Nov. 2008.
[3-8] D. Schroder, Semiconductor material and device characterization:
Wiley-IEEE Press, 2006.
[3-9] K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFET's,” IEEE Trans. Electron Devices, Vol. 33, No. 7, pp.
965-972, Jul. 1986.
[3-10] S. D. Kim, S. Narasimha, and K. Rim, “An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs,” IEDM Tech. Dig., pp.149-152, 2005.
[3-11] J. Appenzeller, Y. M. Lin, J. Knoch, and Ph. Avouris, “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., Vol. 93, No. 19, Nov. 2004.
[3-12] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” IEDM Tech.
- 43 -
Dig, pp. 289-292, 2002.
[3-13] H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, “Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels,” IEEE Trans. Electron Devices, Vol. 53, No. 10, pp. 2471-2477, Oct.
2006.
- 44 -
(a) (b)
Fig. 2-1 Step coverage of deposited film over non-planar topography with (a) conformal and (b) non-conformal deposition.
Deposited Film Deposited Film
- 45 -
(a)
(b)
Fig. 2-2 SEM images of 100 nm-thickness α-Ge thin films deposited on (a) the single side-gated structure and (b) inverse-T-gated structure.
- 46 -
Fig. 2-3 SEM image of a 150 nm-thick α-Ge thin film deposited on the single side-gated structure.
Fig. 2-4 TEM cross-sectional view of poly-Ge film annealed at 500 oC for 1 hour.
The circled area in the image indicates the region of a grain.
α- Ge layer
~ 5 nm
- 47 -
Fig. 2-5 Diffraction pattern of the poly-Ge film.
- 48 -
(a)
(b)
Fig. 2-6 Top views of (a) single side-gated (b) inverse-T-gated poly-Ge NWTFT.
L
Single Side-Gate
Drain
Source
L
Inverse-T-Gate
Drain
Source
- 49 -
Fig. 2-7 (a) Deposition of in situ doped n+ poly-Si on oxide-capped Si substrate.
Fig. 2-7 (b) First gate definition by standard I-line lithography and subsequent dry etching steps.
Si Substrate Thermal Oxide
n
+Poly Si
Si Substrate Thermal Oxide
Gate
(a)
(b)
- 50 -
Fig. 2-7 (c) Second gate definition by standard I-line lithography and subsequent dry etching steps to form the inverse-T-gate.
Fig. 2-7 (d) Deposition of gate oxide and α-Ge layers.
Si Substrate Thermal Oxide
Gate
Si Substrate Thermal Oxide
Gate α - Ge
(c)
(d)
- 51 -
Fig. 2-7 (e) Source/drain ion implantation.
Fig. 2-7 (f) Definition of source/drain and formation of NW channel.
Si Substrate Thermal Oxide
Gate α - Ge
Si Substrate Thermal Oxide
Gate
Source
Drain
Poly – Ge NW Channel
(e)
(f)
- 52 -
Fig. 2-8 Top view of independent double-gated poly-Ge NWTFT.
Fig. 2-9 Deposition of top gate oxide and formation of top gate.
L
Inverse-T-Gate
Drain
Source
Top Gate
Si Substrate Thermal Oxide
Gate Gate Top Gate
Poly – Ge NW Channel
Source
Drain
- 53 -
Fig. 2-10 SEM picture of a fabricated device. Both height and width of NW channel are 45 nm.
Single Side-Gate
Height : ~45 nm
Width : ~45 nm Poly – Ge NW Channel
- 54 -
(a)
(b)
Fig. 2-11 Comparisons of transfer characteristics between inverse-T-gated and Single Side-Gated poly-Ge NWTFTs with channel length of (a) 0.4 and (b) 0.7
- 55 -
Fig. 2-12 Output characteristics of ITG and Single side- gated poly-Ge NWTFTs.
Fig. 2-13 Comparisons of transfer characteristics between poly-Ge planar TFT and poly-Ge NWTFT (ITG : inverse-T-gated).
Drain Voltage (V)
- 56 -
Fig. 2-14 Transfer characteristics of independent DG poly-Ge NWTFT operated in single-gated (SG) modes and double-gated (DG) mode.
Fig. 2-15 Output characteristics of a device under DG mode.
Gate Voltage (V)
- 57 -
- 58 -
Fig. 2-17 Transfer characteristics of DG devices characterized by sweeping inverse-T gate voltage with top gate biased at various constant values.
Fig. 2-18 Extracted Vth as a function of top-gate voltage (ITG : inverse-T-gated).
Gate Voltage (V)
Top - Gate Voltage (V)
-8 -6 -4 -2 0 2 4
- 59 -
(a) (b)
Fig. 3-1 (a) Top view and (b) cross-sectional view of a JL poly-Si NWFET.
Fig. 3-2 Fabrication of the JL device. (a) Deposition of a bottom nitride/TEOS oxide/hardmask nitride stacked layer. The thicknesses were 50/30/30 nm, respectively.
S
D Gate
SSS
DDD Gate
Si Substrate Thermal Oxide
SiN TEOS
SiN
Si Substrate Thermal Oxide
Gate
Doped Poly-Si NW Channel
(a)
- 60 -
Fig. 3-2 (b) The hardmask nitride/TEOS oxide stack was defined by anisotropic reactive plasma etching.
Fig. 3-2 (c) The formation of cavities by utilizing DHF lateral etching.
Si Substrate Thermal Oxide
SiN TEOS
SiN
Si Substrate Thermal Oxide
SiN TEOS
SiN
(b)
(c)
- 61 -
Fig. 3-2 (d) Deposition of in situ phosphorus doped poly-Si layer.
Fig. 3-2 (e) Definition of source/drain and formation of doped poly-Si NW channels.
Si Substrate Thermal Oxide
SiN TEOS
SiN
In Situ Doped
Poly-SiSi Substrate Thermal Oxide
SiN TEOS
SiN
Drain
Source
(d)
(e)
- 62 -
Fig. 3-2 (f) Removal of bottom nitride/TEOS oxide/hardmask nitride stacked layer.
The NW channels are hanging between the S/D regions.
Fig. 3-2 (g) Deposition of a TEOS oxide layer as the gate dielectric.
Si Substrate Thermal Oxide
Drain
Source
Si Substrate Thermal Oxide
TEOS
(f)
(g)
- 63 -
Fig. 3-2 (h) Deposition of a TiN film as the gate electrode.
Fig. 3-3 Fabrication of the IM device. (a) 100 nm amorphous-Si layer deposition followed by 600oC annealing at N2 ambient for 24 HR (SPC).
Si Substrate Thermal Oxide
Gate
Doped Poly-Si NW Cannel
Drain
Source
Si Substrate Thermal Oxide
SiN TEOS
SiN
α-Si
(h)
(a)
- 64 -
Fig. 3-3 (b) Dry etching to form NWs underneath the hard mask.
Fig. 3-3 (c) Deposition of 100 nm in situ phosphorus doped poly-Si layer.
Si Substrate Thermal Oxide
SiN TEOS
SiN
Si Substrate Thermal Oxide
SiN TEOS
SiN
In Situ Doped
Poly-Si(b)
(c)
- 65 -
Fig. 3-3 (d) Definition of S/D regions by dry etching.
Fig. 3-4 Cross-sectional-view TEM picture of a JL-NWFET with GAA structure.
Si Substrate Thermal Oxide
SiN TEOS
SiN
Drain
Source
Undoped Poly-Si NW Cannel
(d)
- 66 -
- 67 -
Fig. 3-6 Measured ION of JL and IM devices as a function of channel length.
Chanel Length (
µµµµm)
0 1 2 3 4 5 6
Drain Current (A)
10
-710
-610
-5JL - NWFETs IM - NWFETs
VG– Vth = 4 V VD= 0.5 V
- 68 -
(a)
(b)
Fig. 3-7 (a) A schematic diagram illustrating the collapse of the suspended NW channels after the surrounding dielectrics were removed during fabrication as the channel length is larger than 1 μm. (b) TEM image of omega-gate.
NW Channel
Omega-Gate (ΩG)
L=2µm
- 69 -
- 70 -
(a)
(b)
Fig. 3-9 Threshold voltage as a function of channel length for (a) JL-NWFETs and (b) IM-NWFETs.
- 71 -
Fig. 3-10 Drain-induced barrier lowering (DIBL) for JL-NWFETs and IM-NWFETs as a function of channel length.
Channel Length (
µµµµm)
0 1 2 3 4 5 6
DIBL (mV)
-200 -100 0 100 200 300 400
JL - NWFETs IM - NWFETs
DIBL=Vth(VD=0.5V)-Vth(VD=2V)
- 72 -
(a)
(b)
Fig. 3-11 The subthreshold swing of (a) JL-NWFETs and (b) IM-NWFETs as a function of channel length.
Chanel Length (
µµµµm)
- 73 -
- 74 -
- 75 -
Fig. 3-14 Subthreshold characteristics and transconductance of JL-NWFET and IM-NWFET versus gate voltage.
Fig. 3-15 Subthreshold characteristics and transconductance as a function of gate overdrive voltage.
Gate Voltage (V)
- 76 -
Fig. 3-16 Comparisons of field-effect mobility for JL-NWFETs and IM-NWFETs.
Fig. 3-17 Extraction of Rtot for JL-NWFETs and IM-NWFETs.
Chanel Length (
µµµµm)
- 77 -
Fig. 3-18 Transfer characteristics with various drain voltages (L= 5 µm).
Fig. 3-19 Extracted Vth and S.S. from Fig. 3-18 as a function of drain voltage.
- 78 -
Publication List
[1] Yu-Ling Liou, Wei-Chen Chen, Horng-Chih Lin, and Tiao-Yuan Huang,
“Fabrication and Characterization of Poly-Germanium Nanowire TFTs,” Int.
Electron Devices and Materials Symp. (IEDMS), Nov. 2010.
[2] Chun-Jung Su, Yu-Ling Liou, Tzu-I Tsai, Horng-Chih Lin, Tien-Shen Chao, and Bing-Yue Tsui, “Fabrication and characterization of junctionless poly-Si nanowire devices with gate-all-around structure,” submitted to International Symposium on VLSI-TSA, 2011.
[3] Chun-Jung Su, Tzu-I Tsai, Yu-Ling Liou, Zer-Ming Lin, Horng-Chih Lin, Tien-Sheng Chao, and Bing-Yue Tsui, “Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels,” submitted to IEEE Electron Device Lett..