K-J Cho Approach

The S-J Jou approach is introduced in last section. In which, the error-compensation bias is generated using statistical analysis and linear regression analysis. And the probability of each partial product bit Pi_j equaling “1” is different for different β and τ. In this section, the second approach, K-J Cho approach [8] [9], will be introduced. In this approach, the error-compensation bias is obtained by using Booth encoder outputs. And the probability of each partial product bit Pi_j equaling “1” is 1/2 for any β and τ.

Table 2-2 shows the values of partial product of 8-bit Booth multipliers. Where

'

2 1 2 2 1

i 2 i i i

b = − ib ₊ +b +b ₋ (2.4)

If the value of bi’ is zero, each bit of partial product “Pi” will be zero. Otherwise, the value of partial product “Pi” will be based on input data “A”.

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-From Fig 2-1, the carry from low part from high part can be expressed as

7 elements in LP_minor.

Fig 2-4 shows the structure of K-J Cho approach. The adder cells of LP_minor are omitted and the error-compensation bias of low part is defined as follow.

[ ]

1

1

E 2 A

Carry_τ− =C ^⎡⎢⎣ β+C λ ^⎤⎥⎦ (2.8) Where CE[t] represents the exact carry value of t and CA[t] means the approximate carry value of t. So, CA[λ] means the approximate carry from LP_minor to LP_major.

Fig 2-4: Structure of K-J Cho scheme In order to find the error-compensation bias, to define yi” as

1, 0

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-four possible values: 1000, 2000, -1000, and -2000. There are only three 8-bit numbers which can have y3”y2”y1”y0” = 1000. Table 2-3 shows the three 8-bit numbers. which are shown as follow

3 2 1 0

The partial products for the three multiplier coefficients corresponding to y3”y2”y1”y0” = 0001 is shown in Fig 2-5. As we have assumed in last section, the probability of each input bit equaling “1” is 0.5. That is

[ ]

2

E ai = (2.11)

Thus, the rounded value of E[λ] for each of the three cases in Fig 2-5 can be computed as follows: other words, the probability of {E[λ]}r equaling “1” is 2/3 which is bigger than 1/2. So, the

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-value of {E[λ]}r can be set to 1 for y3”y2”y1”y0” = 0001.

Notice that E[λ] is always zero for the three 8-bit numbers with y3”y2”y1”y0” = 1000.

Because no element of the partial product corresponding to y3’ is included in LP_minor as can be seen in Fig 2-1. In general, the element of the partial product corresponding to ₁

n2

y′ ₋ is not included in LP_minor for any input width “n”.

Fig 2-5: Partial products for y3”y2”y1”y0” = 0001

From previous discussions, it is obvious that the value of E[λ] is calculated by the LP_minor of partial product. By using K-J Cho approach, to determine the error-compensation bias is more easily. Because the carry from LP_minor to LP_major is replaced by {E[λ]r}, we only need to calculate the values of {E[λ]r} for each case of

n -22

y′′ _{n -3}

y′′2 …y′′ . Then, the circuit of carry generation can be designed based on the values of ₀ {E[λ]r}.

The procedure of K-J Cho approach is explained in the following example.

Example 1: In this example, it will show the process of K-J Cho approach by using a 10 x 10 Booth multiplier. First, we should calculate the values of {E[λ]}r for all the possible values of y3”y2”y1”y0” and the values of {E[λ]}r are shown in Table 2-4. Notice that y′′ is ₄ not shown in Table 2-4 since there is no any element of the partial product corresponding to y4’ is included in LP_minor.

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-Table 2-4: Rounded value of E[λ] for n = 10

Table 2-5: Representation of approximate carry values

In Table 2-4, the biggest value of carry is two. Thus, two approximate carry signals (LP_carry_0 and LP_carry_1) are needed to represent the values of {E[λ]}r.The values of the two carry signals are shown in Table 2-5. We can obtain the circuit of the approximate carry signals by using Karnaugh map as shown in Fig 2-6. In Fig 2-6, the values of approximate carry signals can be determined using probability analysis. For example, for y3”y2”y1”y0” = 0001, P[{E[λ]}r=0] = 4/12 and P[{E[λ]}r=1] = 8/12. Thus, the value of approximate carry signals is determined to be 1. Then, LP_carry_0 and LP_carry_1 signals can be simplified from each map as

Fig 2-7 shows the circuit of equation (2.13) which is the approximate carry signals from LP_minor to LP_major. The approximate carry signals are added to LP_major. Then, the resulted carry signals from LP_major are added to HP as error-compensation bias.

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-Fig 2-6: Karnaugh map representation for (a)LP_carry_0 and (b)LP_carry_1 for n = 10

Fig 2-7: Circuit of approximate carry for n = 10 The procedure of Example 1 is illustrated as below:

I. For given input width “n”, the number of approximate carry signals is determined as NAC = ⎢⎣n/ 4⎥⎦

II. The approximate carry signals are denoted as LP_carry_0, LP_carry_1, … , LP_carry_(NAC - 1)

III. To calculate the rounded values of {E[λ]r} for each case of _{n -2} y′′2 _{n -3}

y′′2 …y′′ . ₀

IV. By applying Karnaugh map to the result in step III, approximate carry generation circuit can be designed.

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-To perform the exhaustive simulation for large width of input data will take a lot of time. A statistical analysis for obtaining the approximate carry values is introduced as below.

Given yi” is 1, it can be shown that E[Pi_j] = 1/2. If y2”y1”y0” = 100 in Fig 2-1, E[λ] can be computed by using equation (2.5)

1 2

In general, E[λ] can be computed by equation (2.14)

1

In the following example, the procedure of this scheme for n = 10 is explained.

Example 2: For n = 10

1

3 2 1 0

[ ] 2 ( )

E λ = ⁻ y′′+y′′+ +y′′ y′′ (2.17) The maximum rounded value of E[λ] is 2. Hence, two signals are needed to represent the rounded value.

If the number of yi ” equaling “1” are one or two, the rounded value is equal to 1. Else if the number of yi” equaling “1” are more than three, the rounded value is equal to 2. Then, the approximate carry generation circuit for n = 10 can be obtain as shown in Fig 2-8(a). Using the same scheme, the approximate carry circuit for n = 14 is shown in Fig 2-8(b).

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-Fig 2-8: Approximate carry generation circuits (a)n = 10 (b)n = 14 The procedure of Example 2 described as below:

I. The signals in the { ₂ added using a HA. For k = 1, the signal in the last group is passed to the next stage. The N (or N+1 for k = 2) carry signals from each adder are approximate carry signals.

III. The sum signals generated in step II are added using the same principle as in step II.

Then, the carry signals from each adder are approximate carry signals. The new sum signals are passed to the next stage.

IV. Repeat step II until only one sum signal is left.

V. Add “1” to the last adder.

The circuit of 8 x 8 fixed-width multiplier with K-J Cho approach is shown in Fig 2-9.

From Fig 2-9, we can find that the adder cells of low part are skipped. The carry from low part to high part is replaced by the approximate carry signals (LP_carry_0 and LP_carry_1) which are generated by Fig 2-8(a).

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-Fig 2-9: Fixed-width multiplier with K-J Cho approach for n = 8