The amplitude of measured current jump (∆Id) versus gate length.
Fig. 3.9
10-3 10-2 10-1 100
Fig 3.10 Step-like channel current evolution during recovery in (a)High-k nMOS(W/L=0.16µm/0.08µm) (b)High-k pMOS (W/L=0.16µm/0.08µm) (c)Oxide nMOS (W/L=0.4µm/
0.18µm) (a)
(c) (b)
0.08 0.12 0.16 0.20 0.24
0.12 0.16 0.20 0.24
0
Fig 3.11 The amplitude of measured current jump(△Id) versus gate length (a)High-k nMOS (b)High-k pMOS (c)Oxide pMOS (a)
(b)
(c)
0.3 0.4 0.5
Recovery Gate Voltage (V)
Emission time (s)
Recovery Gate Voltage (V)
<τ2>
Recovery Gate Voltage (V)
Emission time (s)
Oxide pMOS
Fig 3.12 Vg dependence of average High-k trapped charge emission times τ1,τ2 in recovery phase.(a)High-k nMOS (b)High-k pMOS (c)Oxide nMOS.
(a)
(b)
(c)
2.8 3.0 3.2 3.4
Chapter 4 Conclusion
A fast transient measurement setup and technique is developed in this work. The technique is firstly used to study PBTI recovery transient in HfSiON nMOSFETs.
Single electron emission from traps in HfSiON gate dielectric is observed in small-size devices. Based on the characterization of recovery field and temperature effects on the single electron phenomena, a SRH-like thermally-assisted-tunneling model for trapped charge emission is proposed. The model well explains the experimental results and the prediction it makes is verified by measurement. The extracted trap activation energy is 0.18eV. Results from large- and small-size devices are well correlated. It is found that the trap density can be evaluated self-consistently from the ratio of trapped charge emission times (small devices) and from drain current recovery slope (large devices). The recovery transient for a large-area device is also well reproduced and follows logarithmic time dependence.
Furthermore, the technique is applied to pMOSFETs with high-k and SiO2 as gate dielectric for single hole analysis. Comparison shows the emission mechanism is universal for transient electron/hole de-trapping in high-k and SiO2. It is also found that the role of thermal process (activation energy) depends on material type (high-k or SiO2), not on carrier type (electron or hole). The proposed technique is a powerful tool to characterize traps in gate dielectric for advanced CMOS.
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