Linear Phase Locked Loop

The LPLL ( also known as Analog Phase-Lock Loop (APLL) ) is a traditional PLL as shown in Figure 1.1, which was proposed back in 1930s. Phase Detector (PD) can detect the different phase error between the reference clock and the output clock. PD can be a four phase analog multiplixer or analog signal mixer. Loop Filter (LP) is a filter to filter high frequency signal and noises from PD and environment. The output of Loop Filter is a DC value to send to Voltage Control Oscillator ( VCO) to generate desired frequency. Through the closed feedback loop, the PLL can lock the input reference clock phase and frequency.

1.2.3 Digital Phase Lock Loop

Figure 1.2 shows the DPLL. The components of DPLL are : Digital Phase Frequency Detector (PFD), Analog Charge Pump, Analog Loop Filter, Analog

Voltage Control Oscillator, and Frequency Divider (FD). Phase Frequency Detector can detect the phase and frequency error between Frequency Divider output and input reference clock. The outputs of PFD are Up or Down signals to Charge Pump to charge capacitor. Loop Filter is a kind of low pass filter filtering noise and high frequency signal and send out the DC value to Voltage Control Oscillator. The Phase Frequency Detector can detect rising edge or falling edge to check the phase error.

The output of Phase Frequency Detector can be the value of phase error or high/low (Up/Down) signal to Charge Pump. Phase Frequency Detector can be the basic logic gate (XOR, NAND, OR…,etc.). The input signal of Phase Frequency Detector is square wave but not the sine wave. Frequency Divider circuit make output clock reach a N times rate to reference clock with the same phase. The DPLL is a hybrid system which contains analog and digital design techniques. Designer should have more skills with mixed-signal designs.

Fig. 1-2 DPLL block diagram

1.2.4 All Digital Phase Lock Loop

All Digital Phase-Locked Loop (ADPLL) consists full digital component: Digital

Phase Frequency Detector, Digital Control Unit, Digital Control Oscillator, and Digital Frequency Divider as shown in figure 1-3. An ADPLL does not have any passive component such as capacitor and resistor. All signals in the ADPLL are digital signals. The analog VCO was replaced by the digital VCO. The Phase

Frequency Detector detects the frequency difference and the phase difference between the reference clock and the feedback signal. The Control Unit receives the signals to control the DCO. By including a divide-by –N divider in the feedback path, the DCO clocks runs N times faster than input reference clock. The functional blocks of the ADPLL imitate the functions of the corresponding analog blocks. Because the

ADPLL consists of dgital circuits entirely, they are many different of design methods to achieve the functions of them. The ADPLL system is a discrete-time system, hence analyzing the ADPLL in S-domain is not suitable. The ADPLL system can be analyzed in time-dimain or Z-domain, or building a new model to analyze the ADPLL

system. Because of no analog components, the ADPLL is a very high noise rejection PLL design. The whole system can be designed by basic logic gates.

Table 1-1 Phase-Locked Loop Comparison

LPLL DPLL ADPLL

Design Cycle Slow Slow Fast

Output Frequency High High Low

Noise Rejection Poor Poor Good

Circuit Area Big Big Design

Dependent

Locking Cycle Slow Slow Quick

Design Technique Analog Mixed Signal Digital

1.3 The motivation of research

Fiber optical transmission using a short optical pulse strain is a fundamental technology in order to achieve a high-speed and long distance global network. For ultra-high speed fiber optical communication, the characteristic of ideal transmission source is demanded to be stable, widely tunable wavelength, transform limited, low timing jitter, adjustable pulsewidth, and high extinction ratio. Therefore a mode-locked erbium-doped fiber lasers source with high repetition rate and short pulsewidth is good selection for ultra-high speed communication system. Besides, these ML-EDFLs can produce higher output power and lower insertion loss in all fiber system.

In order to achieve the ML-EDFLs stable for a long time, improving it by PLL circuit is a good method. A Phase-Locked Loop circuit is a modern interesting electronic building block widely applied in electronics and wireless communication systems. As mentioned above, there are several types to realize phase shifter function. Among the versatile investigations, continuously tuning the phase of microwave signal or optical clock via optical or optoelectronic technique has been extensively studied since its particular applications in phased-array antennas (PAAs), wireless or fiber communications and the electro-optic sampling (EOS) system. In electronics, a phase-locked loop (PLL) is a closed-loop feedback control system that maintains a generated signal in a fixed phase relationship to a reference signal. Since an integrated circuit can hold a complete phase-locked loop building block, the technique is widely used in modern electronic devices, with signal frequencies from a fraction of a cycle per second up to many gigahertz. So in my thesis, I will describe how the PLL application in the ML-EDFLs.

1.4 The organization of this thesis

This thesis is consisted four chapters. Chapter 1 introduce the history of laser, PLL and my motivation. In Chapter 2, it will describe the principle of mode locked laser and PLL. In chapter 3, I will present my experiment result and analysis it.

Finally, chapter 4 will give conclusions and improvement.

CHAPTER 2

B ASIC C ONCEPTS

2.1 Theory of the active mode locked laser

2.1.1 Amplitude modulation mode locked

Amplitude modulation mode-locking is a method to produce a short pulse train and high repetition rate by directly modulating the optical amplitude of the light. It can be analyzed both in the time and frequency domains. In the time domain, the amplitude modulation provides a time dependent loss so that only the pulses which pass through the modulator at the lowest loss will exist. As the pulses pass through the modulator continually, the pulsewidth will get shorter and shorter. However, shorter pulses will experience larger dispersion and finally the two forces balance each other to form the steady state pulse shape. In this way, the modulation time period must be equal to a multiple of the roundtrip time for producing stable pulses. Figure 2.1 shows the active mode-locking process in the time domain.

Fig. 2.1 Amplitude modulation in the time domain

In frequency domain, we can assume that the center frequency of signal gain profile is νo, and the amplitude of the central mode without amplitude modulation is expressed as ε(t) = E0 cos(ωot). The transform function of the active amplitude modulator, which controls the loss of light in the cavity, can be written as

and f_m is modulation frequency, such as the signal after modulation can be expressed asfollowing

where ∆m is modulation index. It is clear from this equation that the center frequency νo induces two side modes with fixed phase relationship νo ± fm while it experiences modulation of active modulator. Similarly, after these two side modes which are made by center frequency νo go through the active amplitude modulator, there will also increase other new side modes νo± 2 fm with fixed phase relationship.

These sidebands can injection-lock the neighboring modes sequentially and finally the mode-locking is achieved. (See figure 2.2)

The modes that are separated every fm will be phase-locked, and short pulses can be formed in the time domain. When N equals to 1, the laser is mode locked at the fundamental repetition rate. When N is an integer greater than 1, the laser is harmonic

Fig. 2.2 Principle of actively mode-locking explained in the frequency domain

2.1.2 Phase modulation mode locked

Phase modulation mode-locking is a method to produce a short pulse train by modulating the optical phase. It can also be analyzed both in the time and the frequency domains.

In the time domain, the phase modulator provides a periodic phase change for the optical pulse. If the pulsewidth is much smaller than the modulation period, the change of the optical phase produced by the phase modulator can be expressed as:

where φo is a constant phase, and the influence of φo on optical pulse can be

neglected . The first order term ^d_dt^φ will influence the central frequency of the pulses

and shifting magnitude of influence depends on its value. Therefore, if ^d_dt^φ

t ≠ 0,

the central frequency of optical pulse will be changed. In another word, the pulse will

experience smaller gain and center frequency will still be changed, if ^d_dt^φ

t

is still not equal to zero. This is unstable and will not lase. Only the pulses which pass through

the PM modulator and experience maximum gain is at ^d_dt^φ

t = 0 ,

and its every round trip is able to be stable. Then, it will lase. ( See fig. 2.3)

Fig. 2.3 Time domain of phase modulation

As regarding the second order term ^d_dt²2

t t

2 2

φ

≡ η

, it adds a chirp to the pulse.

Also, it will affect the optical bandwidth of the pulses. The effect can be expressed in mathematics by:

∆ ω = _τ

¹2

+ ητ

²

where

∆ ω

is the bandwidth of optical pulse, τ is the pulsewidth , and

η =

^{d φ}

dt

2 2 is the chirp parameter.

In the frequency domain, we can assume that the central frequency is νo . When it passes through the phase modulator, the electric field of the pulse can be written as:

where fm is the modulating frequency of phase modulator, ∆m is the modulation index, and Jn is the n-th order Bessel function. If νo is one of the harmonic modes in the laser cavity and fm is N times magnitude of the fundamental harmonic frequency of the cavity, these harmonic modes (νo +k fm ) will have the fixed phase relation with the νo , where K=±1, ±2, ±3, , ,etc la. Therefore, all these harmonic modes will have fixed phase relation. In time domain, these harmonic modes will create constructive interference at periodic time and destructive interference at other times by injection-locking.(see fig. 2.4)

Fig. 2.4 Development of pulse train in time domain by superposition of modes

2.1.3 Harmonic mode-locked

A continuous wave erbium ring laser can be actively mode-locked by using an amplitude or phase modulator to generate pulses at the modulation frequency fm

where fc is the cavity mode-spacing frequency, c is the speed of light, L is the cavity length and n is the refractive index of the cavity. These pulses have a round trip time of tr , which is related to fc and the pulse width τ as following,

This is known as fundamental mode-locking, and it produces pulses at repetition rate equal to f_m .The cavity mode-spacing frequency of a typical laser cavity is of the order of 0.5~6MHz. To increase the pulse repetition rate, pulses could be produced at integer harmonics of the cavity mode-spacing by modulating at a frequency fm , given by

where P is an integer representing the number of longitudinal modes locked, and ranges from a few hundred to tens of thousand. This is known as harmonic mode locking, these longitudinal modes with equal interval Pf_p is called as supermodes, and its new round trip time shows as following,

In 1970s, the KS theory predicted that with amplitude mode-locking the time

bandwidth product is 0.441 for a chirp-free Gaussian pulse and 0.315 for a Sech² pulse.

Furthermore, it states that the pulsewidthτis inversely proportional to ( )δ ¹⁴ and

(f • ∆f )¹⁴ , so that

where δ is the effective single-pass amplitude modulation depth, ∆f_3dB is the 3dB gain band width of the laser cavity and K is a pulse shape-dependent constant. It is clear from this equation that with increasing modulation frequency and increasing modulation amplitude, the optical pulsewidth will be narrowed.

However, though we can use this way to promote higher repetition rates, the drawback of harmonic mode-locking is not stable for a long time. We will discuss it later.

Actually, the smallest pulsewidth and chirp of the pulses can be estimated by using the time-bandwidth product of transform limited. For chirp free Gaussian sharp, time bandwidth product is 0.441. For Sech²sharp, time bandwidth product is 0.315.

We can use this transform-limited to appraise our laser. However, the exact estimate is not possible since the cavity dispersion is not considered in equation (a).

2.2 Theory of the PLL circuit

2.2.1 PLL basics

Phase locked loop has three basic components ; a phase detector ,a loop filter , a voltage-controlled oscillator.

The phase detector is a device that produces a measure of the difference in phase between an incoming signal and the local replica .As the incoming signal and the local replica change with respect to each other, then the phase difference becomes a time-varying signal into the loop filter. The loop filter governs the PLL＇s response to these variation in the error signal . The VOC device that produces the carrier replica . The voltage control oscillator , as the name implies ,is a sinusoidal oscillator whose freq. is controlled by a voltage level at the device input.

Fig. 2.5 Phase lock loop basic component

‧ Basic idea of a phase-locked loop:

– inject sinusoidal signal into the reference input

– the internal oscillator locks to the reference

– frequency and phase differences between the reference and internal sinusoid

⇒ k or 0

– Internal sinusoid then represents a filtered version of the reference sinusoid.

– For digital signals, Walsh functions replace sinusoids.

2.2.2General PLL block diagram

Fig. 2.6 Phase lock loop block diagram

‧ A phase detector (PD). This is a nonlinear device whose output contains the phase difference between the two oscillating input signals.

‧ A voltage controlled oscillator (VCO). This is another nonlinear device which produces an oscillation whose frequency is controlled by a lower frequency input voltage.

‧ A loop filter (LF). While this can be omitted, resulting in what is known as a first order PLL, it is always conceptually there since PLLs depend on some sort of low pass filtering in order to function properly.

‧ A feedback interconnection. Namely the phase detector takes as its input the reference signal and the output of the VCO. The output of the phase detector, the phase error, is used as the control voltage for the VCO. The phase error may or may not be filtered.

2.2.3Unique features of the PLLs as control loops

‧ Correct operation depends on being nonlinear. Phase detector action (frequency to phase) and VCO action (phase to frequency) are nonlinear. Different parts of loop are in different spaces (signal response and phase response).

‧ PLLs are almost always low order (not counting various high frequency filters and parasitic poles). Typically first or second order. A few third or fourth order loops.

‧ With the exception of PLL controlled motors, the PLL designer is responsible for designing/specifying all the components of the feedback loop. Complete feedback loop design replaces control law design, and the designer’s job is governed only by the required characteristics of the input reference signal, the required output signal,and technology limitations of the circuits themselves.

‧ PLL control of motors, the motor and optical coupler takes the place of the VCO.

The rest is at the designer＇s discretion.

‧ Control theory used in most PLL texts is straight linear system design with a small amount of nonlinear heuristics thrown in.

‧ Stability analysis and design of the loops is combination of linear analysis, rule of thumb, and simulation.

‧ Experts in PLLs tend to be electrical engineers with hardware design backgrounds.

‧ General theory of PLLs and ideas on how to make them even more useful seems to cross into the controls literature only rarely.

2.3 Math for PLL

2.3.1Typical simplifying steps

Fig. 2.7 Phase lock loop math type

‧ General sinusoid at reference input can be written as:

‧ Assume VCO output signal is

‧ Mixer output is

where Km is the gain of the mixer

Now I can use the familiar trigonometric identity in terms of PLL:

(4)

Two fundamental assumptions lead to common analog PLL model. Let θd = θi – θo.

Then the assumptions are :

1 ) The first term in (4) is attenuated by the high frequency low pass filter in and by

the low pass nature of the PLL itself.

2 ) Let ωi ≈ ωo, so that the difference can be incorporated into θd. This means that the VCO can be modeled as an integrator.

3 ) The baseband phase detector output is then:

2.3.2Standard nonlinear model for analog PLL

Fig. 2.8 Phase lock loop nonlinear model

As show as fig. 2.4, it still a nonlinear system. The typical analysis methods include:

1) Linearization: For θd small

sin θd ≈ θd and cos θd ≈ 1.

Useful for studying loops that are near lock, does not help when θd is large.

2) Phase plane portraits. Classical graphical method of analyzing behavior of low order nonlinear systems about a singular point. Can only completely describe first and second order systems.

3) Simulation. Explicit simulation of the entire PLL is relatively rare. Problem is stiff.

Simulations that sample fast enough to characterize the 2ω_ot term are often far too

response space.

⇒ Simulate the entire loop only in signal phase space.

2.3.3Standard linear model for analog PLLs

Fig. 2.9 Phase lock loop linear model

Used for most analysis and measurements of PLLs. Model has some omissions:

1) The texts typically omit the input bandpass filter.

‧ Not in the loop itself & the actual input frequency is often not known or is variable.

‧ The designer has some idea of the range of the signal.

‧ Input bandpass filter can considerably reduce broadband noise entering the system.

2) The texts typically omit the high frequency low pass filter. The loop filter is optimized for the stability and performance of the baseband (phase).

3) Amplitude of the phase error is dependent upon A( Mixer output ), the input signal amplitude. The linearized model has a loop gain that is dependent upon the loop components. Thus, in practical loop design, the input amplitude must either be regulated or its affects on the loop must be anticipated.

CHAPTER 3

E XPERIMENTAL SETUP AND RESULTS

3.1 Introduction of my experiment setup

My experiment utilizes the active mode locked fiber laser to generate short pulsewidth, high output power, and repetition rate 10G pulsetrain. To make pulsetrain steady, I use the phase locked loop application in my experiment. As my thesis describe previously , PLL has three basics；phase detector , low pass filter , and voltage control oscillator . In my experiment, the phase detector is a double balance mixer, the low pass filter is a RC circuit, and the voltage control oscillator is the PZT.

The double balance mixer has two inputs and one output. In these two inputs, one is the signal of the ring and another is the synthesizer signal, and then this output delivers into the low pass filter. When it passes through the low pass filter, only the frequency difference between incoming and local signal can pass. Finally the difference of the frequency term will control the PZT to match the length at the right time. Because the PZT is a fiber which can change its length by input voltage, this three basics will describe clearly in latter section.

3.1.2 Double balance mixer

Introduction

The double balance mixer is not only a phase detector but also a frequency detector. However, in my experiment, the double balance mixer is just for a phase detector. The double balance mixer has two inputs and one output. (See fig.3.1)

These two inputs one is LO port and another is RF port. The output is the IF port. We assume LO port signal is A1sin(ω¹ t+Φ¹) and RF port signal is A2sin(ω² t+Φ²). The output IF port signal is 1/2A1 A2sin[(ω¹ t –ω²t) +(Φ¹–Φ²)] and 1/2A1

A2sin[(ω¹ t +ω²t) +(Φ¹+Φ²)]. So the double balance mixer is also a multiplier.

Fig. 3.1 structure of the double balance mixer Operation

The double balance mixer is a passive device, so the operation is easily.

What we need to pay attention to is take care of the RF and LO port, which available frequency range is 6~18G Hz. The frequency range of the IF port is DC~3000M Hz.

Also the LO port input power operates about 10dBm.

Performance

As what I described previously, the double balance is a frequency detector. I use 6G Hz signal to test it. Table 3.1 is the result.

Double

LO (Hz) 6.0000G 6.0000G 6.0000G 6.0000G 6.0000G

Table 3.1 result of the double balance mixer

By the same token, the double balance mixer is the phase detector. I used the synthesizer to connect the RF and LO port, but the LO port was added a delay line.

Then I measure the IF port variation when I change the delay time. When I change the phase from 0 to 2πby the delay line. We can find that the IF output with variation of phase induced variation of voltage. (See Table 3.2)

Table 3.2 variation of voltage by changed the delay line

3.1.3 Low pass filter

Introduction

A low-pass filter passes low frequencies fairly well, but attenuates, or blocks,

LO RF IF (Vpp)

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