The measurement waveforms of SCR structure are shown in Fig. 4.10. After ESD stress, the current of SCR structure is pulled up and the voltage of Vdd is pulled down. As the result, the circuit is latchup. The results of SCR structure with noise filter (with decoupling capacitance and TVS) are shown in Fig. 4.11 and Fig. 4.12.
The TLU level is higher when SCR structure aids with capacitor. As the value of capacitor increasing, the TLU level is developed. And the TLU level is more significant in negative ESD stress.
The measurement waveforms of ring oscillator are shown in Fig. 4.13. After ESD stress, the output of the ring oscillator is failed to meet the function. IDD significantly increases with the pull-down Vdd due to a low-impedance latching path between Vdd and ground. The results of ring oscillator with noise filter (decoupling capacitance and TVS) are shown in the Fig. 4.14 and 4.15. The TLU levels are different between positive and negative ESD stress. Positive TLU level is higher than negative TLU level.
The measurement waveforms of transient detection circuit are shown in Fig. 4.16.
When ESD stress occurs, Vdd will be interrupt. The output of the circuit (out1 and out2) will be pulled up. This result means that the circuit memorizes the occurrence of ESD stress. The results of transient detection circuit with noise filter are shown in table 4.1. The detection levels are different between positive and negative ESD stress.
The circuit is much more sensitive to negative ESD stress than to positive ESD stress.
4.4 C
ONCLUSIONBy choosing proper components in each noise filter network, the TLU immunity of CMOS ICs under the system-level ESD stresses can be greatly improved. From the experimental results, the decoupling capacitor not only can enhance TLU level, but also is compatible to CMOS technology for integrating the noise filter into chips.
Therefore, the decoupling capacitor is better than TVS for being a noise-bypassing component in the noise filter networks. The measurement results that the EUT are much more sensitive to negative ESD stress than to positive ESD stress. The result consists with the TLU in CMOS ICs under system-level ESD test [7] [8].
As the measurement results, the positive ESD voltage level acting transient detection circuit is much larger than negative one. This phenomenon could be verified by different parasitic capacitances of the pad, which is shown in Fig. 4.17. The simulation result is shown in Fig. 4.18 to 4.21. The parasitic capacitances of Vdd and Gnd pads of Fig. 4.18 and 4.19 are the same (case 1: C1 = 8pF, C2 = 5 pF, L1 = 8 nH, C3 = 16 pF, C4 = 10 pF, and L2 =16 nH), and the noise peaks are + 20 V and – 20 V.
The responses of the transient detection circuit are different. The parasitic capacitances of Fig 4.20 and 4.21 are the same (case 2: C1 = 16pF, C2 = 10 pF, L1 = 16 nH, C3 = 8 pF, C4 = 5 pF, and L2 =8 nH), but the values are different in Fig 4.18 and 4.19. The noise peaks are + 20 V and – 20 V at Fig 4.20 and 4.21. From the simulation results, different parasitic capacitances of Vdd and Gnd pad do affect the function of the transient detection circuit.
In order to make sure the character of TVS, the parasitic capacitance of TVS is shown in Fig. 4.22. The parasitic capacitance of TVS is too small to improve such ESD voltage. Therefore, the parasitic capacitance of TVS is not a major reason to protect the device under test.
Table 4.1 The measurement result of transient detection circuit under ESD stress.
Fig. 4.1 Die photo of the transient detection circuit.
Fig. 4.2 Layout view of the transient detection circuit.
Fig. 4.3 Measurement setup of the system-level ESD test with indirect contact-discharge test mode.
Fig. 4.4 Measurement instruments.
Fig. 4.5 Top view of PCB photo.
Fig. 4.6 Measured Vdd, IDD and OUT waveforms of the ring oscillator, for the ESD gun with ESD voltage of – 800 V zapping on the HCP.
Fig. 4.7 Noise filter network.
Fig. 4.8 (a) Device cross-sectional view and (b) layout top view of the SCR structure for system-level ESD test.
VDD
101-Stage Inverter Chain 7-Stage Taper Buffer
VDD1
Fig. 4.9 (a) Circuit diagram and (b) layout top view of the oscillator circuit for system-level ESD test.
Fig. 4.10 Measurement waveform of SCR structure under ESD stress.
0.1 1 10
Decoupling Capacitance ( μ F )
Negative TLU Level of SCR1 Positive TLU Level of SCR1 Negative TLU Level of SCR2 Positive TLU Level of SCR2
W/O Cap.
0.9 kV 0.8 kV 0.5 kV 0.3 kV
Fig. 4.11 Correlations between measurement TLU levels and decoupling capacitances with two SCR structures.
5 10 15 20 25 30
0 1 2
TLU Level (kV)
Breakdown Voltage of TVS (V)
Negative TLU Level of SCR1 Positive TLU Level of SCR1 Negative TLU Level of SCR2 Positive TLU Level of SCR2
Fig. 4.12 Correlations between measurement TLU levels and breakdown voltages of TVS with two SCR structures.
Fig. 4.13 Measurement waveforms of the ring oscillator circuit under ESD stress.
10-1 100 101 102 103
1 2 3
TLU Level (kV)
Decoupling Capacitance (
μF )
Negative TLU Level Posgative TLU Level
Fig. 4.14 Correlations between measurement TLU levels and decoupling capacitances with ring oscillator.
15 20 25 30
Breakdown Voltage of TVS (V)
Negative TLU Level
Fig. 4.15 Correlations between measurement TLU levels and breakdown voltage of TVS with the ring oscillator.
ESD Voltage: -1.5 kV
Fig. 4.16 Measurement waveforms of transient detection circuit under ESD stress.
Fig. 4.17 Parasitic capacitances of power pads.
Fig. 4.18 Simulation results of the transient detection circuit with – 20 V noise voltage (case 1).
Vdd
Fig. 4.19 Simulation results of the transient detection circuit with + 20 V noise voltage (case 1).
Fig. 4.20 Simulation results of the transient detection circuit with – 20 V noise voltage (case 2).
Vdd
Gnd
Out1
Out2
3.3 V
3.3 V Reset
0 V
0 V 0 V
0 V
0 V
3.3 V
0 V
0 V 3.3 V 0 V 0 V
3.3 V
3.3 V
Fig. 4.21 Simulation results of the transient detection circuit with + 20 V noise voltage (case 2).
Fig. 4.22 The parasitic capacitance of TVS.