Fig. 5-4 shows the die photo of our circuits. The decouple capacitors are inserted to minimize the noise on power and ground lines. Fig. 5-5 demonstrates the PCB (Printed Circuit Board) photo. The input and output pins are placed near the core, so the signals suffer less decay from metal wiring. The measurement setup is depicted in Fig. 5-6. Keiethley 2400 and Agilent E3610A are used to provide the supply voltage for the ADPLL core and the output buffers respectively. Agilent 81130A Pulse Data Generator provides the input reference clock for the ADPLL. At last, we use Agilent 54832D Mixed-Signal Oscilloscope to observe the output waveforms of the ADPLL and the frequency divider output. It can be used to measure the timing jitter as well.
Fig. 5-4: Die photo
Fig. 5-5: PCB layout
Fig. 5-6: Measurement Setup
5.3 Measured Results
In this section, we present the measured results of our ADPLL design. Fig. 5-7 shows the free-running of the DCO at 0.5V supply voltage. The free-running frequency is 586 MHz.
Fig. 5-7: DCO free-running @ 0.5V
Then we measure the different locking frequencies at the supply voltage of 0.5V, and observe the output jitter of 10K hits. Fig. 5-8 shows the output waveforms and jitter measured result of the ADPLL locked at 240 MHz. The peak-to-peak jitter is 105 ps. When the ADPLL is locked at 320 MHz, the output jitter is 76.4 ps as depicted in Fig. 5-9. As for the 400 MHz output in our design, the peak-to-peak jitter is 69.1 ps as shown in Fig. 5-10 and the power consumption is 70 µW. Fig. 5-11 shows the output waveform and the peak-to-peak jitter when ADPLL is locked at 480 MHz.
Fig. 5-8: ADPLL locked @ 240 MHz
Fig. 5-10: ADPLL locked @ 400 MHz
Fig. 5-11: ADPLL locked @ 480 MHz
The jitter performance and the power consumption at different operation frequency can be depicted in Fig. 5-12. Table 5-3 shows the measured results under different supply voltages.
Based on the measurement results above, the chip summary is given in Table 5-4.
200 250 300 350 400 450 500
Fig. 5-12: Power consumption and jitter at different frequency
Table 5-3: Output performance of different supply voltage VDD = 0.4 V
Table 5-4: Chip summary
Process UMC 90nm
Supply Voltage (V) 0.5
DCO Type Ring
Locking Range (MHz) 240 ~ 480
Peak-to-peak Jitter (ps) 69.1 @ 400 MHz
Power Consumption ( Wµ ) 70 @ 400 MHz
Core Area (mm2) 0.057
5.4 Comparison
Table 5-5 presents the comparison of our ADPLL with other papers in recent years.
Owing to different process and operation frequency, it is not easy to compare the measurement specifications. So the FOM (Figure of Merit) is utilized. According to [16], the FOM of PLL is given by
1
FOM [mW][ jitter(ps) mW ]
= GHz × . (5.1)
Furthermore, if we take process and chip area into consideration, the FOM can be modified by
2
Based on the FOMs numbers, we can conclude that the ADPLL in our design takes advantage of the low power consumption and has much more superior performance than the other works.
Finally, the FOM comparisons are illustrated in Fig. 5-13 and Fig. 5-14.
Table 5-5: Comparison table
500 1000 1500 2000 2500 3000
Fig. 5-13: FOM1 versus operation frequency
500 1000 1500 2000 2500 3000
0.1
Fig. 5-14: FOM2 versus operation frequency
Chapter 6
Conclusion
In this thesis we have proposed an ADPLL with bootstrapped DCO. With the bootstrapped delay cell in DCO, the driving ability under low power supply environment is improved. Besides, it has better the linearity versus the control voltage and the process variation in different process corner is decreased as well. On the other hand, the 9-bit DCO with 4-bit SDM dithering enhances the equivalent DCO resolution without much hardware overhead. Finally the proposed ADPLL is fabricated in UMC 90nm CMOS process.
According to the measured result, the core area is 0.057mm2, and the output locking range is 240 ~ 480 MHz under 0.5V power supply. While locked at 400 MHz, the output peak-to-peak jitter is 69.1 ps and the power consumption is 70 µW.
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