Summary

Negative bias temperature instability of p-channel LTPS TFTs has been studied in this article, and we have proved NBTI is important in the reliability of LTPS TFTs. It is found the threshold voltage, subthreshold swing, maximum transconductance and drive current of LTPS TFTs degrade after NBTI stress. The device degradation caused by NBTI stress increases with temperature and electric field, indicating NBTI can be thermally and electrically activated. Due to the grain boundaries in the channel regions of LTPS TFTs, the grain boundaries trap state generation must be considered during NBTI stress. In this study, it is proved the threshold voltage shift is closely related to the grain boundary trap state generation, because both the two physical quantities follow almost the same power low dependence on the stress time; moreover, exponential dependence on the stress voltage and reciprocal of the ambient temperature. The exponent value of the power law dependence on the stress time is about 1/4 to 1/3, which is explained by the diffusion-controlled electrochemical reactions. Besides threshold voltage shift, NBTI also leads to the degradation of subthreshold swing, driving current and hole mobility. From the experimental results, we concluded that NBTI is caused by the generation of fixed oxide charges, interface states and grain boundary trap states in LTPS TFTs. Furthermore, a physical model is proposed and verified by the experimental results.

REFERENCES

[1] Tadashi Serikawa and Fujio Omata, “High-Quality Polycrystalline Si TFTs Fabricated on Stailess Foil by Using Sputtered Si Films,” IEEE Trans.

Electron Devices, vol. 49, pp. 820-825, 2002.

[2] Tadashi Serikawa, Seiiti Shirai, Akio Okamoto and Shiro Suyama,

“Low-Temperature Fabrication of High-Mobility Poly-Si TFT’s for Large-Area LCD’s,” IEEE Trans. Electron Devices, vol.36, pp. 1929-1933, 1989.

[3] I-Wei Wu, Warren B. Jackson, Tiao-Yuan Huang, Alan G. Lewis and Anne Chiang, “Mechanism of Device Degradation in n- and p-Channel Polysilicon TFT’s by Electrical Stressing,” IEEE Electron Device Lett., vol. 11, pp.

167-170, 1990.

[4] C. E. Blat, E. H. Nicollian and E. H. Poindexter, “Mechanism of negative-bias-temperature instability,” J. Appl. Phys., vol. 63, pp. 1712-1720, 1991.

[5] Shigeo Ogawa and Noboru Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO₂ interface,” Phys.

Rev. B, vol. 51, pp. 4218-4230, 1995.

[6] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller and T.

Horiuchi, “NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.1-µm gate CMOS generation,” in Symp. VLSI Tech. Dig., 2000, pp. 92-93.

[7] Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, pp. 1-18, 2003.

[8] Kousuke Okuyama, Katsuhiko Kubota, Takashi Hashimoto, Shuji Ikeda and

Atsuyosi Koike, “Water-Related Threshold Voltage Instability of Polysilicon TFTs,” in IEDM Tech. Dig., 1993, pp. 527-530.

[9] S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M.

Ashida, T. Muragishi and T. Nishimura, “NEGATIVE BIAS TEMPERATURE INSTABILITY IN POLY-Si TFTs ,” in Symp. VLSI Tech.

Dig., 1993, pp. 29-30.

[10] Anand T. Krishnan, Vijay Reddy and Srikanth Krishnan, “Impact of Charging Damage on Negative Bias Temperature Instability,” in IEDM Tech. Dig., 2001, pp. 39.3.1-39.3.4.

[11] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai and T.

Horiuchi, “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” in Symp. VLSI Tech. Dig., 1999, pp. 73-74.

[12] M. J. Powell, C. van Berkel and J. R. Hughes, “Time and temperature dependence of instability mechanisms in amorphous silicon thin-film transistors,” Appl. Phys. Lett., vol. 54, pp. 1323-1325, 1989.

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Rider, “Conductivity behavior in polycrystalline semiconductor thin film

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598-605, 1992.

[19] Kjell O. Jeppson and Christer M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. Appl.

Phys., vol. 48, pp. 2004-2014, 1977.

(a) Buffer layer deposition .on glass substrate.

(b) Amorphous Si (a-Si) deposited by PECVD.

(c) Crystallization of a-Si film into poly-Si film by excimer laser annealing, and active region defined.

Glass Buffer Layer

Glass Buffer Layer

a-Si

Glass

Buffer Layer

Poly-Si Channel

(d) Deposition .of gate oxide by PECVD

(e) Deposition Mo as the gate electrode.

Glass Buffer Layer Poly-Si Channel

Gate Oxide

Glass Buffer Layer Poly-Si Channel

Gate Oxide

Metal Gate

(f) Self-align Source/Drain was formed.

(g) Interface layer deposition and dopant activation..

Glass Buffer Layer Poly-Si Channel

Gate Oxide Metal Gate

P

⁺

P

⁺

Glass Buffer Layer Poly-Si Channel

Gate Oxide Metal Gate

P

⁺

P

⁺

(h) Contact holes was opened and inter-connection metal was deposited and patterned.

Glass Buffer Layer Poly-Si Channel

Gate Oxide Metal Gate

P

⁺

P

⁺

(i) Schematic cross-section diagram of LTPS TFT and NBTI stress setup. The stress temperature was performed from 25^oC to 150^oC, and the stress gate

voltage was applied in the range of -15V to -30V with source and drain grounded.

Fig. 2-1 Process flow of the poly-Si TFT.

-10^-13

Fig. 2-2(a) Transfer characteristics of LTPS TFT before and after 1000sec NBTI stress at 100^oC with the stress voltage of -30V.

-4 10^-5

-3 10^-5

-2 10^-5

-1 10^-5

0

-4 -3

-2 -1

0

Drain Curre n t, I

DS

(A)

Drain Voltage, V

DS

(V)

VGS= - 4V W/L=20um/10um

Stress Condition Temperature=100^oC Stress Time=1000s VG=-30V

Full : initial Hollow : stress

VGS= - 3V

VGS= - 2V

Fig. 2-2(b) Output characteristics of LTPS TFT before and after 1000sec NBTI stress at 100^oC with the stress voltage of -30V.

0.001 0.01 0.1 1

0.1 1 10 100 1000

VG=-15V VG=-20V VG=-25V VG=-30V

-V

th

Sh ift (V)

Stress Time (s)

W/L=20um/10um Temperature=100^oC

Fig. 2-3(a) Dependences of threshold voltage shift on the stress time of LTPS TFTs under various stress conditions.

0.01 0.1 1 10

25^oC 50^oC 100^oC 150^oC

-35 -30

-25 -20

-15 -10

-V

th

Sh ift (V)

Gate Voltage, V

G

(V)

W/L=20um/10um Stress Time=1000s

Fig. 2-3(b) Dependences of threshold voltage shift on the stress voltage of LTPS TFTs under various stress conditions.

0.01 0.1 1 10

26 28 30 32 34 36 38 40

VG=-15V, Ea~0.13eV VG=-20V, Ea~0.14eV VG=-25V, Ea~0.14eV VG=-30V, Ea~0.16eV

- V

th

Shift (V)

1/kT (1/eV)

W/L=20um/10um Stress Time=1000s

Fig. 2-3(c) Dependences of threshold voltage shift on the stress temperature of LTPS TFTs under various stress conditions.

0.1 1 10 100 1000 10⁴ 10⁵ 10⁶

-35 -30

-25 -20

-15 -10

25^oC 50^oC 100^oC 150^oC

Li fet ime @ V

th

Shift=-1 00mV (s ec)

Gate Voltage, V

G

(V)

Fig. 2-4. Dependences of lifetime on the stress voltage with various stress temperatures. The lifetime is defined as the time taken to reach a threshold voltage shift of 100mV.

Fig. 2-5(a) Correlation between the degradation of subthreshold swing, and threshold voltage shift of LTPS TFTs after NBTI stress.

0 10 20 30 40 50 60 70 80

-1 -0.8

-0.6 -0.4

-0.2 0

150^oC 100^oC

S.S. D e g ra d a tio n (% )

V

th

Shift (V)

-10

-8

-6

-4

-2

0

-1 -0.8

-0.6 -0.4

-0.2 0

150^oC 100^oC

G

m,max

De g rad ation (%)

V

th

Shift (V)

Fig. 2-5(b) Correlation between the degradation of maximum transconductance, and threshold voltage shift of LTPS TFTs after NBTI stress.

-15.8 -15.6 -15.4 -15.2 -15 -14.8 -14.6 -14.4

0.02 0.04 0.06 0.08 0.1

inital stress

ln [ I

DS

/( V

GS

-V

FB

)]

1/(V

GS

-V

FB

)

²

(V

^-2

)

Stress Condition Temperature=100^oC Stress Time=1000s VG=-30V

Ntrap=5.9*10¹¹cm^-2

Ntrap=8.1*10¹¹cm^-2

Fig. 2-6. Grain boundary trap state density extraction of LTPS TFT before and after 1000 sec NBTI stress at 100^oC with the stress voltage of -30V.

10⁹ 10¹⁰ 10¹¹ 10¹²

0.1 1 10 100 1000

VG=-15V VG=-20V VG=-25V VG=-30V

N

trap

G e ner a ted (cm

-2

)

Stress Time (s)

W/L=20um/10um Temperature : 100^oC

Fig. 2-7. Dependences of grain boundary trap state density variation on the stress time at 100^oC with various stress gate voltages.

0

0 10 20 30 40 50 60 70 80

-1 -0.8

-0.6 -0.4

-0.2 0

100^oC 150^oC 25^oC 50^oC

N

trap

Varia ti o n (%)

V

th

Shift (V)

Fig. 2-9. Correlation between grain boundary trap state density variation and threshold voltage shift of LTPS TFTs after NBTI stress.

10⁹ 10¹⁰ 10¹¹ 10¹² 10¹³

10⁹ 10¹⁰ 10¹¹ 10¹² 10¹³

150^oC 100^oC

G e ner a te d N

it

(c m

-2

)

Generated N

trap

(cm

^-2

)

Fig. 2-10. Correlation between the generation of interface state density and grain boundary trap state density of LTPS TFTs after NBTI stress.

-60

Fig. 2-11. Dependences of drive current degradation on the stress voltage with various stress temperatures.

Fig. 2-12. Energy band diagram of p-channel LTPS TFT under NBTI stress.

Chapter 3

Plasma Damage Enhanced Negative Bias Temperature Instability in Low Temperature

Polycrystalline Silicon Thin Film Transistors

3.1 Introduction

Recently, low temperature polycrystalline silicon thin film transistors (LTPS TFTs) have attracted much research interest. Due to its’ high carrier mobility, the integration of driving circuits and pixels on a glass substrate can be performed, realizing system on panel (SOP) [1]. To achieve good process repetitiousness and precisely controlled of feature sizes, plasma process has been widely used in the manufacture of ULSI and LTPS TFTs. However, plasma damage has been reported to degrade the performance and reliability in thin film transistors [2]-[4].

In p-channel metal-oxide-semiconductor field effect transistors (PMOSFETs), negative bias temperature instability (NBTI) has been widely studied and found to be an important reliability issue [5] [6]. Additionally, it has been reported that plasma damage leads to severe NBTI in PMOSFETs [7]-[10]. In thin film transistors, several researchers have showed NBTI occurs as well as in PMOSFETs [11] [12]; however, the correlation between plasma damage and NBTI in LTPS TFTs has not been explored.

The purpose of this study was to investigate the effect of plasma damage on the NBTI behaviors in LTPS TFTs. Devices were designed with various antenna

structures, and NBTI stress was performed on the devices to inspect the effect of plasma damage.

3.2 Experimental

P-channel LTPS TFTs were fabricated on glass substrates in this study. First, a 40nm-thick amorphous-Si layer was deposited and crystallized into poly-Si film by excimer laser annealing. After defining the active region, the gate dielectric was deposited with an equivalent 100nm-thick SiO2 layer. Then, Mo was deposited and patterned as the gate electrode. Following source/drain formation, inter-layer dielectric was deposited and densified. Finally, inter-connection metal was deposited and patterned. The channel length (L) and width (W) of the devices mainly used were 10 and 20µm, respectively. The metal pads attached to the gate were designed with antenna area ratio (AR) of 100, 500 and 1000. The AR is defined as the ratio between antenna area and gate area on active region (L×W). The schematic cross-section diagram of the test structure is shown in Fig. 3-1. NBTI stress was performed at 150^oC, and stress voltage of -30V was applied to the gate with source/drain grounded.

3.3 Results and Discussion

Figure 3-2 shows NBTI induced transfer characteristic degradation for the LTPS TFTs with AR of 100, 500 and 1000, respectively. We found that NBTI stress will make the threshold voltage (Vth) shift to negative direction and simultaneously degrade the subthreshold swing (S.S.); additionally, the effects are getting worse for the devices with larger AR. According to the results shown in Fig. 3-2, it is reasonable to assume that the NBTI effects are highly correlated to the plasma damage in LTPS TFTs. The correlations can be further observed from the threshold voltage shift (∆Vth)

vs. the stress time for the LTPS TFTs with different AR drawn in Fig. 3-3, which significantly presents a fact that a larger AR do induce a greater ∆Vth. It has been demonstrated that the NBTI induced Vth shift in MOSFET is mainly caused by the generation of interface states and fixed oxide charges [5] [6]. In highly matching with the NBTI phenomena in LTPS TFTs, we can speculate that the plasma damage enhances threshold voltage shift due to higher generation rate of interface states and fixed oxide charges. Compared with the∆Vth, the on current (ION) degradation rates revealed in Fig. 3-4 present the same trend that confirms the proposed mechanisms.

It is well known that the ∆Vth of PMOSFETs under NBTI stress shows a power law dependence on the stress time, which can be explained by the diffusion-controlled electrochemical reactions [13] [14]. From the Fig. 3-5, we found that the ∆Vth of LTPS TFTs under NBTI stress also follows similar dependency on the stress time. Figure 3-6 exhibits the extracted exponent factors (n) for LTPS TFTs with different AR; it presents an interesting result that the value of n is getting larger for the device with higher AR. This result indicates that the plasma damage accelerates NBTI degradation in LTPS TFTs.

Figures 3-7 and Fig. 3-8 compares ln [I_DS/ (V_GS-V_FB)] vs. 1/ (V_GS-V_FB)² curves for the fresh and NBTI stressed LTPS TFTs with AR of 100 and 1000. The grain boundary trap state density (Ntrap) can be estimated by Levinson and Proano method [15] [16]. Form the figure, it is found that Ntrap is increased from 7.8×10¹¹ to 1.5×10¹² (cm^-2) for the device with AR of 100, and from 9.1×10¹¹ to 1.3×10¹² (cm^-2) for the device with AR of 1000. In summary, the overall generation rate of Ntrap is enhanced for devices with larger AR; this signifies that plasma damage enhances NBTI not only through the previously mentioned mechanisms, but also by accelerating the generation rate of grain boundary trap states.

Table 3-1 compares the parameter variation of LTPS TFTs with AR of 100, 500

and 1000 under 1000 sec NBTI stress. As AR increases, the device shows more degradation in field effect mobility (µeff), S.S. and Vth. This implies that the plasma damage enhances NBTI stress by increasing the generation rate of both interface states and fixed oxide charges. Moreover, plasma damage also enhanced the generation rate of Ntrap under NBTI stress. It could be concluded that the plasma damage is an important factor for NBTI degradation in LTPS TFTs.

3.4 Summary

In this study, we have confirmed that plasma damage is a significant factor for NBTI in LTPS TFTs. The experimental results show that the consequence of plasma damage will be presented under NBTI stress. The accelerating phenomena is mainly attributed to the generation rate increment of interface states, grain boundary trap states and fixed oxide charges. Therefore, in sustaining the LTPS TFTs with both the high reliability and yield, the antenna structures must be carefully designed.

Reference

[1] Tadashi Serikawa, Seiiti Shirai, Akio Okamoto and Shiro Suyama,

“Low-temperature fabrication of high-mobility poly-Si TFT’s for large-area LCD’s,” IEEE Trans. Electron Devices, vol. 36, pp. 1929-1933, 1989.

[2] Kan Yuan Lee, Yean Kuen Fang, Chii Wen Cheng, Kou Chin Huang, Mong Song Liang and Sou Gow Wuu, “Impact of hydrogenating plasma induced oxide charging effects on the characteristics of polysilicon thin film transistors,” Jpn. J.

Appl. Phys. vol. 36, pp. 1025-1029, 1997.

[3] Jiun-Jye Chang, Chih-Chiang Chen, Ching-Sang Chuang, Yung-Fu Wu, Chai-Yuan Sheu, Yung-Hui Yeh and Nan-Chou Liu, “Characteristics of dry etch process stability and damage recovery ability on LTPS TFTs,” in AMLCDs Tech.

Dig., 2003, pp. 87-90.

[4] Chih-Yang Chen, Shen-De Wang, Ming-Shan Shieh, Wei-Cheng Chen, Hsiao-Yi Lin, Kuan-Lin Yeh, Jam-Wen Lee and Tan-Fu Lei, “Process induced instability and reliability issues in low temperature poly-Si thin film transistors,” in Proc.

IRPS, 2006, pp. 713-714.

[5] C. E. Blat, E. H. Nicollian and E. H. Poindexter, “Mechanism of negative-bias-temperature instability,” J. Appl. Phys., vol. 63, pp. 1712-1720, 1991.

[6] Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability:

road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl.

Phys., vol. 94, pp. 1-18, 2003.

[7] Felino E. Pagaduan, J. K. Jerry Lee, Veena Vedagarbha, Kenneth Lui, Michael J.

Hart, Daniel Gitlin, Tomoo Takaso, Shinya Kamiyama and Keiichi Nakayama,

“The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance,” in Proc. IRPS, 2001,

pp. 315-318.

[8] Anand T. Krishnan, Vijay Reddy and Srikanth Krishnan, “Impact of charging damage on negative bias temperature instability,” in IEDM Tech. Dig., 2001, pp.

865-868.

[9] Noriaki Matsunaga, Hitomi Yoshinari and Hideki Shibata, “NBTI analysis of antenna pMOSFET with thermally recovered plasma-induced damage,” in Porc.

7^t Int. Symp. Plasma- and Process-Induced Damage , 2002, pp. 142-145.

[10] Da-Yuan Lee, Horng-Chih Lin, Meng-Feng Wang, Min-Yu Tsai, Tiao-Yuan Huang and Tahui Wang, “Enhanced negative-bias-temperature instability of p-channel metal-oxide-semiconductor transistors due to plasma charging damage,” Jpn. J. Appl. Phys., vol. 41, pp. 2419-2422, 2002.

[11] Kousuke Okuyama, Katsuhiko Kubota, Takashi Hashimoto, Shuji Ikeda and Atsuyosi Koike, “Water-related threshold voltage instability of polysilicon TFTs,” in IEDM Tech. Dig., 1993, pp. 527-530.

[12] S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M.

Ashida, T. Muragishi and T. Nishimura, “Negative bias temperature instability in poly-Si TFTs,” in Symp. VLSI Tech. Dig., 1993, pp. 29-30.

[13] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai and T. Horiuchi,

“The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” in Symp. VLSI Tech. Dig., 1999, pp. 73-74.

[14] Shigeo Ogawa and Noboru Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface,” Phys. Rev. B, vol. 51, pp. 4218-4230, 1995.

[15] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este and M. Rider,

“Conductivity behavior in polycrystalline semiconductor thin film transistors,” J.

Appl. Phys., vol. 53, pp. 1193-1202, 1982.

[16] R. E. Proano, R. S. Misage and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistor,” IEEE Trans. Electron Devices, vol. 36, pp. 1915-1922, 1989.

Fig. 3-1 The schematic cross-section diagram of the test LTPS TFT structure.

Source (p

⁺

) Drain (p

⁺

) Gate

Antenna (Metal Pad)

Inter-Layer Dielectric

Gate Dielectric

Buffered Layer

Glass Substrate

10^-13 10^-12 10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5

-4 -3 -2 -1 0 1

initial AR=100 AR=500 AR=1000

Dra in C u rr e n t, I

DS

(A )

Gate Voltage, V

GS

(V)

Stress

Stress Condition Temperature = 150^oC Stress Time = 1000s VG = -30V

VDS= - 0.1V

Fig. 3-2 Transfer characteristics of LTPS TFT with AR of 100, 500 and 1000 before and after 1000sec NBTI stress.

-1

-0.8

-0.6

-0.4

-0.2

0

0 200 400 600 800 1000

AR = 100 AR = 500 AR = 1000

V

th

S h ift (V )

Stress Time (s)

Stress Condition Temperature = 150^oC VG = -30V

Fig. 3-3 Dependence of threshold voltage shift on the stress time of LTPS TFTs with AR of 100, 500 and 1000.

-40

-35

-30

-25

-20

-15

-10

-5

0

0 200 400 600 800 1000

AR = 100 AR = 500 AR = 1000

I

ON

D e g rad at io n R a te ( % )

Stress Time (s)

Temperature = 150^oC VG = -30V

Fig. 3-4 Dependence of on current degradation rate on the stress time of LTPS TFTs with AR of 100, 500 and 1000.

0.1 1

0.1 1 10 100 1000

AR=100 AR=500 AR=1000

y = 0.10078 * x^(0.29854) R= 0.99815 y = 0.11004 * x^(0.29991) R= 0.99869 y = 0.10679 * x^(0.3336) R= 0.99919

V

th

Sh if t (V)

Stress Time (s)

Temperature = 150^oC VG = -30V

Fig. 3-5 The linear fit of the log-log plot of the threshold voltage shift versus the stress time of LTPS TFTs with AR of 100, 500 and 1000 under NBTI stress.

0.2 0.25 0.3 0.35 0.4 0.45 0.5

Ex pon e n t Fa c to r, n

Area Ratio, AR

100 500 1000

Stress Condition Temperature = 150

^o

C V

G

= -30V

Fig. 3-6 Exponent factor n of LTPS TFTs with various AR.

-26 -24 -22 -20 -18 -16 -14

0 0.12 0.24 0.36 0.48 0.6

inital stress

ln [ I

DS

/( V

GS

-V

FB

)]

1/(V

GS

-V

FB

)

²

(V

^-2

)

AR = 100

Stress Condition Temperature = 150^oC Vg = -30V

Time = 1000s

Ntrap = 9.1 X 10¹¹(1/cm²)

Ntrap = 1.3 X 10¹²(1/cm²)

Fig. 3-7 Extraction of grain boundary trap state density of LTPS TFTs with AR of 100 before and after 1000 sec NBTI stress.

-26 -24 -22 -20 -18 -16 -14

0 0.2 0.4 0.6 0.8 1

inital stress

ln [ I

DS

/( V

GS

-V

FB

)]

1/(V

GS

-V

FB

)

²

(V

^-2

)

AR = 1000

Stress Condition Temperature = 150^oC Vg = -30V

Time = 1000s

Ntrap = 7.8 X 10¹¹(1/cm²)

Ntrap = 1.5 X 10¹²(1/cm²)

Fig. 3-8 Extraction of grain boundary trap state density of LTPS TFTs with AR of 1000 before and after 1000 sec NBTI stress.

Table 1

AR=100 AR=500 AR=1000

µ

△ eff (%) -6.7 -7.9 -9.0

△S.S.(%) 52.3 64.2 78.7

△Vth (V) -0.84 -0.91 -1.02

I

△ ON (%) -25.8 -28.3 -32.5

△Ntrap(%) 42.7 67.8 96.3

Table 3-1 Comparison of parameter variation of LTPS TFTs with AR of 100, 500 and 1000 after 1000 sec NBTI stress.

Chapter 4

Combined Negative Bias Temperature Instability and High Current Injection Stress Effects in Low

Temperature Poly-Si Thin Film Transistors

4.1 Introduction

Low temperature poly-Si thin film transistors (LTPS TFTs) are now widely investigated for their potential application in active matrix liquid crystal displays (AMLCDs) and realization of system on panel (SOP). For the LTPS TFTs to be used in advanced analog and mixed signal circuit, the electrical stability becomes an important issue. In the pervious studies, NBTI induced device parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies.

NBTI induced threshold voltage shifts in p-channel TFTs is a critical issue for these analog circuits. To determine maximum threshold voltage (Vth) shift in an analog circuit over its operating lifetime, several factors that influence the conventional DC lifetime projection method need to be considered. Factors such as operating gate and drain voltage impact the DC lifetime extracted from conventional reliability

measurements.

In this chapter, Vth shift due to NBTI and hot carrier injection (HCI) stress in p-channel LTPS TFTs is examined. It is observed that Vth shift are much greater under HCI stress conditions of V_g = V_d =V_stress than under NBTI stress conditions of V_g

=Vstress, Vd =0. This is indicating a greater degree of trap generation under HCI stress.

Moreover, due to the poor conductivity of the buffer oxide, we suppose the temperature dependency of HCI stress induced degradation is an important reliability concern in LTPS TFTs, and compared with NBTI stress.² To quantify the combined NBTI and HCI induced degradation, we proposed a modified model based on the empirical NBTI and HCI models, and the experimental results conformed to the model. Therefore, we can clearly identify the combined NBTI and HCI effects on p-channel LTPS TFTs.

4.2 Experimental

P-channel LTPS TFTs fabricated on glass substrates were used in this work. A 40nm-thick amorphous silicon layer was deposited on a buffer layer by PECVD at 300^oC. The silicon layer was then crystallized into polycrystalline silicon film by excimer laser annealing. Gate dielectric was deposited with an equivalent 100nm-thick SiO2 layer and followed by Mo deposition as the gate electrode. After gate patterning, source and drain were doped by plasma doping. Then, the inter-layer dielectric was deposited and densified. Finally, inter-connection metal was deposited and patterned. Both the channel length (L) and width (W) of the device used in this work were 20µm.

The NBTI stress was performed with VG of -20V, and the stress temperature was kept at 25 or 100^oC. The VDS was varied from 0 to -20V to study the combined NBTI

The NBTI stress was performed with VG of -20V, and the stress temperature was kept at 25 or 100^oC. The VDS was varied from 0 to -20V to study the combined NBTI

在文檔中 低溫複晶矽薄膜電晶體之負偏壓溫度不穩定研究 (頁 35-0)