Organization of the Thesis

In the following sections, we will show our research efforts.

In Chapter 2, we proved NBTI is an important reliability issue in LTPS TFTs, and demonstrated the degradation of LTPS TFTs under NBTI stress is closely related to trap state creation. Measurements revealed the threshold voltage shift is highly correlated to the generation grain boundary trap states.

In Chapter 3, the impact of plasma damage on NBTI in LTPS TFTs is explored.

The experimental results confirm that LTPS TFTs with larger antenna degrade more than those with smaller antenna. Plasma damage is demonstrated to enhance the device degradation in carrier mobility, threshold voltage and drive current under NBTI stress.

In Chapter 4, we investigated degradation mechanism of LTPS TFTs upon NBTI stress and HCI stress. To quantify the combined NBTI and HCI stress induced degradation, we proposed a modified model based on the empirical NBTI and HCI stress models, and the experimental results conformed to the model.

References

[1] M. Makabe, T. Kubota, and T. Kitano, IEEE Int. Reliability Phys. Symp. 38 205, 2000

[2] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J. Electrochem. Soc. 114, 266, 1967.

[3] B. E. Deal, J. Electrochem. Soc. 121, 198C,1974.

[4] A. Goetzberger, A. D. Lopez, and R. J. Strain, J. Electrochem. Soc. 120, 90,1973.

[5] C. H. Fa, and T. T. Jew, “The polysilicon insulated-gate field-effect transistor,”

IEEE Trans. Electron Devices, vol. 13, no. 2, pp. 290, 1966.

[6] Y. Oana, “Current and future technology of low-temperature poly-Si TFT-LCDs,”

Journal of the SID, vol. 9, pp. 169-172, 2001.

[7] S. Morozumi, K. Oguchi, S. Yazawa, Y. Kodaira, H. Ohshima, and T. Mano, “B/W and color LC video display addressed by poly-Si TFTs,” SID Dig, pp.156, 1983.

[8] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Guest-host active matrix liquid-crystal display using high-voltage polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 38, pp. 1781, 1991.

[9] S. Batra, “Development of drain-offset (DO) TFT technology for high density SRAM’s,” Extended Abstracts, vol.94-2, in Electrochemical Soc. Fall Mtg., Miami Beach, FL, Oct. pp. 677,1994.

[10] M. Cao, et al., “A simple EEPROM cell using twin polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 15, pp. 304, 1994.

[11] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, pp.

1930-1936, 1996.

[12] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and system-on-chip integration,” Proceedings of the IEEE, vol.89, pp. 602-633, 2001.

[13] W. G. Hawkins, “Polycrystalline-silicon device technology for large-area electronics,” IEEE Trans. Electron Devices, vol. 33, pp. 477-481, 1986.

[14] H. Kuriyama et al., “Enlargement of poly-Si film grain size by excimer laser annealing and its application to high-performance poly-Si thin film transistor,”

Jpn. J. Appl. Phys., vol. 30, pp. 3700-3703, 1991.

[15] A. Nakamura, F. Emoto, E. Fujii, and A. Tamamoto, “A high-reliability, low-operation-voltage monolithic active-matrix LCD by using advanced solid-phase growth technique,” IEDM Tech. pp.847, 1990.

[16] G. K. Guist, and T. W. Sigmon, “High-performance laser-processed polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 77-79, Feb.

1999.

[17] N. Kudo, N. Kusumoto, T. Inushima,and S. Yamazaki, “Characterization of polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, vol. 40, pp. 1876-1879, Oct. 1994.

[18] S. W. Lee, T. H. Ihn, and S. K. Joo, “Fabrication of high-mobility p-channel poly-Si thin-film transistors by self-aligned metal-induced lateral crystallization,”

IEEE Electron Device Lett., vol. 17, no. 8, pp. 407-409, Aug. 1996.

[19] C. E. Blat, E. H. Nicollian and E. H. Poindexter, “Mechanism of

negative-bias-temperature instability,” J. Appl. Phys., vol. 63, pp. 1712-1720, 1991.

[20] Shigeo Ogawa and Noboru Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface,” Phys. Rev. B, vol.

51, pp. 4218-4230, 1995.

[21] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller and T.

Horiuchi, “NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.1-µm gate CMOS generation,” in Symp. VLSI Tech. Dig., 2000, pp. 92-93.

[22] Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability:

Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl.

Phys., vol. 94, pp. 1-18, 2003.

[23] C. E. Blat, E. H. Nicollian and E. H. Poindexter, “Mechanism of negative- bias-temperature instability,” J. Appl. Phys., vol. 63, pp. 1712-1720, 1991.

[24] Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability:

road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl.

Phys., vol. 94, pp. 1-18, 2003.

[25] Felino E. Pagaduan, J. K. Jerry Lee, Veena Vedagarbha, Kenneth Lui, Michael J.

Hart, Daniel Gitlin, Tomoo Takaso, Shinya Kamiyama and Keiichi Nakayama,

“The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance,” in Proc. IRPS, 2001, pp. 315-318.

[26] Anand T. Krishnan, Vijay Reddy and Srikanth Krishnan, “Impact of charging damage on negative bias temperature instability,” in IEDM Tech. Dig., 2001, pp.

865-868.

[27] Noriaki Matsunaga, Hitomi Yoshinari and Hideki Shibata, “NBTI analysis of antenna pMOSFET with thermally recovered plasma-induced damage,” in Porc.

7^t Int. Symp. Plasma- and Process-Induced Damage , 2002, pp. 142-145.

[28] Da-Yuan Lee, Horng-Chih Lin, Meng-Feng Wang, Min-Yu Tsai, Tiao-Yuan Huang and Tahui Wang, “Enhanced negative-bias-temperature instability of p-channel metal-oxide-semiconductor transistors due to plasma charging damage,” Jpn. J. Appl. Phys., vol. 41, pp. 2419-2422, 2002.

[29] Kousuke Okuyama, Katsuhiko Kubota, Takashi Hashimoto, Shuji Ikeda and Atsuyosi Koike, “Water-related threshold voltage instability of polysilicon TFTs,”

in IEDM Tech. Dig., 1993, pp. 527-530.

[30] S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, T. Ichiki, J. Mitsuhashi, M.

Ashida, T. Muragishi and T. Nishimura, “Negative bias temperature instability in poly-Si TFTs,” in Symp. VLSI Tech. Dig., 1993, pp. 29-30.

[31] Dieter K. Schroder, “Semiconductor Material and Device Characterization,”

Wiley-INTERSCIENCE, 1998

[32] J. Levinson, G. Este, M. Rider, P. J. Scanlon, F. R. Shepherd, and W. D.

Westwood, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, no. 2, pp. 193, 1982

[33] J. Y. W. Seto, “The electrical properties of polycrystalline silicon films,” J. Appl.

Phys., vol. 46, no. 12, pp. 5247, 1975

[34] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin film transistors,” IEEE Trans.

Electron Devices, vol. 36, no. 9, pp. 1915, 1989.

Chapter 2

Characteristic of Negative Bias Temperature Instability in Low Temperature Polycrystalline

Silicon Thin Film Transistors

2.1 Introduction

Polycrystalline silicon thin film transistors (poly-Si TFTs), the key devices for the use in the flat panel displays such as active matrix liquid crystal displays (AMLCDs), have attracted much research interest due to the possibility of realizing the integration of peripheral circuit and active matrix [1][2]. From the fabrication technology point of view and as a long-term reliability concern, the stability of poly-Si TFTs is of significant importance [3]. In p-channel MOSFETs, negative bias temperature instability (NBTI) has been found to be an important reliability problem and has been widely investigated. It has been reported the degradation of NBTI in MOSFETs is mainly due to the generation of interface states and fixed oxide charges, and NBTI can be thermally and electrically activated[4]-[7]. In poly-Si TFTs, due to poor thermal conductivity of the glass substrate and high operation voltage, we suppose NBTI is important in the reliability of poly-Si TFTs. Some researches have pointed out NBTI stress caused the performance degradation in poly-Si TFTs as well as in MOSFETs [8][9].

However, NBTI is still not thoroughly studied in poly-Si TFTs and the mechanism is not well known. In addition, the degradation mechanism of NBTI stress in

poly-Si TFTs, due to the grain boundaries in the channel region, may be different from MOSFETs. Some studies have indicated that NBTI stress on poly-Si TFTs may generate trap states in the grain boundaries [9]. However, the correlation between the grain boundary trap state generation and the device degradation during NBTI stress in poly-Si TFTs has not been well explored.

In this chapter, the instabilities and mechanisms of p-channel low temperature poly-Si TFTs (LTPS TFTs) upon NBTI stress were studied. By measuring and analyzing the transfer and output characteristics before and after NBTI stress under different stress gate voltages and stress temperatures, we investigated the effects of NBTI in LTPS TFTs and proposed a new model to explain the experimental results.

2.2 Experimental

P-channel LTPS TFTs were fabricated on glass substrates with top-gate structures. In this study, a 40nm-thick a-Si layer was deposited by PECVD on a buffer layer and crystallized into poly-Si film by excimer laser annealing. After defining the active region, the gate dielectric was deposited with an equivalent 100nm-thick SiO₂ layer. Mo was then deposited and patterned as the gate electrode. Self-align source/drain was formed by plasma doping. Following that, the inter-layer dielectric was deposited and densified. The hydrogen atoms were also introduced during the deposition of the inter-layer dielectric to passivate the dangling bonds at the poly-Si/SiO₂ interface and in the grain boundaries. The dopants were activated during the densification of the inter-layer dielectric.

Finally, inter-connection metal was deposited and patterned. The channel length (L) and channel width (W) of the device used in this study were 10um and 20um,

respectively.

During NBTI stress, the glass substrate was heated to the stress temperature ranging from 25^oC to 150^oC, and the stress voltage in the range of -15V to -30V was applied the gate with the source/drain grounded. The stress was periodically stopped to measure the basic characteristics of the device to characterize the NBTI effect. All the measurements were taken at the stress temperature.

Fowler-Nordheim current was not pronounced at these bias conditions; therefore, the extra trap state generation and device instability caused by the small current can be neglected. The schematic cross-section diagram of the LTPS TFT and NBTI stress setup is shown in Figure 2-1.

2.3 Results and Discussion

Figure 2-2(a)(b) show the transfer characteristics and output characteristics, respectively, of LTPS TFT before and after NBTI stress at 100^oC with the stress gate voltage of -30V for 1000sec. From Figure 2-2(a), it is observed the threshold voltage becomes larger in the negative direction after NBTI stress. In MOSFETs, the threshold voltage shift is attributed to the generation of fixed oxide charges and interface states [4]-[7]. In poly-Si TFTs, however, there are many grain boundaries in the channel regions and must be considered. Therefore, we suggested the threshold voltage shift in poly-Si TFTs is attributed to the generation of grain boundary trap states as well as the fixed oxide charges and interface states, and this will be discussed later.

In addition to the threshold voltage shift, NBTI stress also leads to the degradation of LTPS TFTs in subthreshold swing (S.S.), drive current (I_ON), and maximum transconductance (Gm,max).

Two parameters leading to the degradation of I_ON and G_m.max are the threshold voltage (Vth) shift and field-effect mobility (µeff) decrease. The decrease of maximum transconductance indicates the field-effect mobility was degraded during the NBTI stress. The drain current significant decreased after NBTI stress as shown is Figure 2-2(b), which is due to the threshold voltage shift and field-effect mobility degradation.

Figure 2-3(a)(b)(c) show the dependence of the threshold voltage shift (ΔV_th) on the stress time (t) , stress voltage (VG) and stress temperature (T), respectively.

The gate voltage at a specified threshold drain current (I_DS), -(W/L)×10nA for VDS=-0.1V, is taken as the threshold voltage. In Figure 2-3(a), the threshold voltage shift increases with the stress time and shows power law dependence. In Figure 2-3(b) and (c), it is observed NBTI will be enhanced at higher stress voltage or higher stress temperature, demonstrating NBTI can be electrically and thermally activated.

The behavior of the threshold voltage shift can be modeled as [10]

a kT CVG

n E

th

t e e

V ∝

^{(− / )}

∆

---(Eq.2.1) where the exponent factor n is around 0.28 to 0.34 in our experiment, which is similar to the results of previous researches in poly-Si TFTs [8][9] and bulk MOSFETs [11]. The parameter C extracted from Figure 2-3(b) is between 0.10 and 0.13, which is dependent on the process and independent of stress voltage.

The activation energy (Ea) extracted from the Arrhenius plot of Fig. 2-3(c) is about 0.14eV.

It is important to distinguish whether the devices degradation under NBTI stress is due to charge trapping in the gate dielectric or due to state creation. In some models of charge trapping in gate dielectric [12], it is revealed that when the

device is under gate bias stress, charges may inject into the gate dielectric and generate extra trap states, leading to the threshold voltage shift. From the previous studies, the threshold voltage shift caused by charge trapping process shows exponential dependence on 1/V-G and virtually temperature independent [12][13].

If the V_th shift is caused by charge trapping, it should have the same dependence on the stress gate voltage and stress temperature as the charge trapping model.

However, the charge trapping model can’t explain the exponential dependence of threshold voltage shift on VG and 1/T as shown in Fig. 2-3(b) and (c), respectively.

Besides, the charge trapping models [12] can’t explain the linear fit of the log-log plot of the threshold voltage shift versus the stress time as shown in Fig. 2-3(a). In addition, the gate leakage current is less than the detection limit, which implies NBTI degradation is not related to the energetic holes [14]. Therefore, instead of charge trapping in the dielectric, we suggested the threshold voltage shift during NBTI stress is due to the state creation in the gate dielectric or channel region.

The lifetimes of LTPS TFTs are plotted as a function of the stress voltage with various stress temperatures as shown in Fig. 2-4. The lifetime is defined as the time taken for the device to reach a threshold voltage shift of 100mV under NBTI stress. Obviously, the lifetime degrades with the increase of stress voltage or temperature because NBTI can be electrically and thermally activated.

Fig. 2-5(a) and (b) reveal the correlation between the degradation of subthreshold swing, maximum transconductance, respectively, and the threshold voltage shift. The generation of interface states is reflected in both the subthreshold swing and maximum transconductance degradation. Furthermore, it has been reported that the subthreshold swing is more closely related to the trap states located near the midgap (deep states), while the mobility is more associated with the trap states located near the band edge (tail states) [15]. The deep states

and tail states originate from the dangling bonds and strain bonds, respectively. In addition, the degradation of subthreshold swing is found to be severer than maximum transconductance degradation; accordingly, we suggested NBTI causes the generation of interface states, and the interface state creation is mainly attributed to the formation of dangling bonds.

Due to the grain boundaries in the channel region, the degradation mechanism of NBTI stress in LTPS TFTs may be different from MOSFETs. In MOSFETs, it has been reported NBTI is mainly due to the generation of interface states and fixed oxide charges [4]-[7]. In order to study the effects of the grain boundaries in LTPS TFTs during NBTI stress, the grain boundary trap state density (N_trap) before and after stress were estimated by Levinson and Proano method [16][17]. Fig. 2-6 exhibits the plots of ln[IDS/(VGS-VFB)] versus 1/(V_GS-V_FB)² curves at low V_DS and high V_GS. The grain boundary trap state density can be determined form the square root of the slope

Slope q

N_trap =C^OX . ---(Eq.2.2)

From Fig. 2-6, it is apparent the grain boundary trap state density increased after NBTI stress, indicating grain boundary trap state generation plays an important role in NBTI stress for LTPS TFTs. Therefore, in addition to the generation of fixed oxide charges and interface states, we have proved the threshold voltage shift of LTPS TFTs under NBTI stress is closely related to grain boundary trap state creation.

In order to learn more about the generation of grain boundary trap states, the dependence of the grain boundary trap state density variation on the stress time is shown in Fig. 2-7. The grain boundary trap state density variation, like the threshold voltage shift, also follows a power law dependence on the stress time

with an exponent of 0.25 to 0.32, which is similar to the exponent factor extracted from Fig. 2-3(a). This means the, threshold voltage shift and grain boundary trap state generation show the same dependence on the stress time. In addition, we also studied the dependence of the grain boundary trap state density variation on the stress voltage and stress temperature (not shown here). It is found the grain boundary trap state density variation has the same function form as the threshold voltage shift, and the grain boundary trap state density variation can be represented as The parameters n’, E_a’, C’ under various NBTI stress conditions are shown in Fig. 2-8, and compared with n, Ea, and C extracted from the threshold voltage shift. It is worth noting that n’, Ea’ and C’ are similar to n, E_a and C, respectively, which implies the grain boundary trap state generation and the threshold voltage shift show the same dependence on the stress time, stress voltage and stress temperature.

Fig. 2-9 illustrates the correlation between the grain boundary trap state density variation and threshold voltage shift, and both of the two physical quantities are closely related because they have the same dependence on the stress time, stress voltage and stress temperature as discussed above. Therefore, we have demonstrated the grain boundaries trap state generation is closely related to the threshold voltage shift during NBTI stress in LTPS TFTs.

In the channel region, we suggested the generation of trap states in the grain boundaries and near the poly-Si/SiO2 interface occurs during NBTI stress. In order to study the correlation between the generations of the grain boundary trap states and trap states near the poly-Si/SiO2 interface, by neglecting the depletion

capacitance in the active layer, the effective interface trap state density (N_it) near the poly-Si/SiO2 interface can be evaluated from the subthreshold swing (S.S.) [18]

Fig.2-10 shows the correlation between the generation of effective interface trap state density (N_it) near the poly-Si/SiO₂ interface and grain boundary trap state density (Ntrap). It is observed the generation rates of Ntrap and Nit during NBTI stress were almost the same. As a result, it is proved the grain boundary trap state generation during NBTI stress is accompanied with the trap state generation near the poly-Si/SiO₂ interface.

Fig.2-11 shows the dependence of the drive current degradation on the stress voltage after 1000sec NBTI stress with various stress temperatures. Due to the threshold voltage shift and mobility degradation, the drive current decreased with NBTI stress. In addition, NBTI can be thermally or electrically accelerated, thus the drive current decreases drastically at elevated stress temperature or higher stress gate voltage.

In our experiment, both the threshold voltage shift and grain boundary trap state generation have almost the same power-law dependence on the stress time.

The exponent value is about 1/4 to 1/3, which is explained by the diffusion-controlled electrochemical reactions [5][19]. By expanding the model proposed for bulk-Si MOSFETs [19], we proposed a new model to explain the effect of NBTI on LTPS TFTs as shown in Fig. 2-12. We assume the Si dangling bonds at the poly-Si/SiO2 interface and in the grain boundaries were passivated by hydrogen atoms initially. During NBTI stress, hydrogen atoms, being weakly bonded to the Si atoms, reacted with the holes from the inversion layer and

dissociated from the Si atoms, resulting in the generation of interface states and grain boundary trap states. The released hydrogen species (atomic or molecular, or ionic or neutral) reacted with SiO₂, leaving positive fixed oxide charges in SiO₂. Finally, the hydrogen species diffused in SiO2, which became the reaction-limiting factor.

2.4 Summary

Negative bias temperature instability of p-channel LTPS TFTs has been studied in this article, and we have proved NBTI is important in the reliability of LTPS TFTs. It is found the threshold voltage, subthreshold swing, maximum transconductance and drive current of LTPS TFTs degrade after NBTI stress. The device degradation caused by NBTI stress increases with temperature and electric

Negative bias temperature instability of p-channel LTPS TFTs has been studied in this article, and we have proved NBTI is important in the reliability of LTPS TFTs. It is found the threshold voltage, subthreshold swing, maximum transconductance and drive current of LTPS TFTs degrade after NBTI stress. The device degradation caused by NBTI stress increases with temperature and electric

在文檔中 低溫複晶矽薄膜電晶體之負偏壓溫度不穩定研究 (頁 22-0)