Chapter 4 Hardware Implementation
4.2 Modules Design
4.2.1 CFO Mitigation Module Design
The proposed architecture of CFO mitigation is shown as Fig. 4.2.
CFO Mitigation
7 ...
Stream1 pilot 0 ( )*
7 ...
Stream2 pilot 0 ( )*
η D
Á[ ]
Â[ ]
Real Divider
>>
To CORDIC
The proposed CFO algorithm has the main advantage of low complexity as mention in chapter 2. To further reduce the area consumptions, we note a feature that CFO mitigation operates during receiving preambles and PET and MIMO detection work during receiving data portion. For this reason, all the main components i.e. the two marked complex multipliers and the real divider shown in Fig.4.2 can share the hardware resources with MIMO detection and PET respectively, so it achieves very low complexity in hardware.
4.2.2 Channel Estimation Module Design
Fig. 4.3 shows the architecture of the proposed tri-mode channel estimation.
l
Figure 4.3 Tri-mode architecture of channel estimator
The algorithms of channel estimation were introduced in chapter 2. We observe
that the operation in Equation (2.9) can be totally included in Equation (2.13) so shared architectures of channel estimation is used for three modes. The estimated channel frequency response (CFR) is then sent to a smoothing FIR filter with three taps [0.25 0.5 0.25] for SISO mode, or is saved to RAM without smoothing for SDM-MIMO and STBC-MIMO modes on the other hand.
4.2.3 Phase Error Tracking Module Design
The proposed architecture of CFO tracking is shown as Fig. 4.4. Same as the steps of the proposed algorithm mentioned in chapter 2, we divide the architecture to three portions, i.e. pilot pre-compensation, phase estimation and recursive adjustment.
In the pilot pre-compensation portion, the phases of pilots in both data streams are compensated using CORDIC modules. After pilot pre-compensation, the detected pilot phase is the difference between two adjacent OFDM symbols. In the phase estimation portion, the architectures of the weighted average phase estimation for SISO mode and the mean average phase estimation for SDM-MIMO/STBC-MIMO modes are combined together. In addition to mean average phase estimation, there are only two de-multiplexers are addition to the proposed architecture. Most of the components are shared, so this architecture increases little complexity in hardware.
Finally, in the recursive adjustment, error vector at current symbol is calculated and the estimated residual CFO is updated. Using the relationship mentioned in equation (2.26), the estimate of SCO can be obtained from CFO. Then the total phase error is sent back to pilot pre-compensation for next symbol duration and is sent to CORDIC modules outside to correct phase errors in data potion.
,1,mrpYl+ 1,ˆ ,2,mkj mrkYelf l+-- +
,2,mrpYl+
[]Á [] Â
0m ml+1,ˆmklf
+-1,ˆ ,1,
mkj mrkYelf l+-- + ˆmla+ ˆ mlf+1ˆmla+-
mlf+1ˆmla+-ml+Q
,1,ˆmkul+ ,2,ˆmkul+
ˆ mul+ mla+¢
1
tan
- 2d
ˆ
mla
+Figure 4.4 The proposed Tri-mode CFO tracker architecture
4.2.4 MIMO Detection Module Design
The channel matrix coefficients of the k-th subcarrier are given by:
1, 3, Equation (4.1) can be re-written as:
1 3 From Equation (2.37), the MMSE filter for SDM-MIMO is:
1 1
We can re-write Equation (4.3) as
* * * * * * * * * * where a is the reciprocal of SNR per receiver, and we ignore the effect of
a
2because it is relatively small. The output after MMSE filter can be written as ˆ ( ) H ( )
X k
=G Y k
× (4.6) In SISO mode transmission, all the channel frequency responses of h2, h3 and h4 are zeros. We observe Equation (4.5) can be simplified as zero forcing for SISO mode1
ˆ ( ) Y k( )
X k
=h
(4.7) On the other hand, STBC detection for STBC-MIMO can be expressed as0 0
The output of STBC detection can be written as
0 0
From above derivation, we can find some similarity between MMSE detection and STBC detection. Both detections need channel coefficients
h
12+h
2 2+h
32+h
4 2, and 2x2 matrix multiplications are required. From above observations, the proposed tri-mode MIMO detection is shown as Fig. 4.5.Figure 4.5 Tri-mode MIMO Detector architecture
While designing the proposed architecture, we notice that the channel coefficients
2 2 2 2
1 2 3 4
h
+h
+h
+h
and matrix multiplier can be shared in hardware. The coefficients which MMSE and STBC need are calculated first at the beginning, and then are sent to divider and matrix multipliers. The incoming data are first divided by g as given in Equation (4.5), and then pass through matrix multiplier for SISO and SDM-MIMO modes. In STBC-MIMO mode, some additional operations are needwhile receiving. Data is encoded across symbols so a delay line is needed to save data of last symbol. An extra matrix multiplier and an adder are also needed for 2x2 STBC operations in ML MIMO detection. To further reduce the complexity in hardware, we note that there is only one operation in MMSE/STBC coefficients calculation during a packet length so the additional matrix multiplier (lower position in the Fig. 4.5) can share complex multipliers with coefficients calculation block for STBC-MIMO mode.
4.2.5 CORDIC Module Design
CORDIC is used for phase rotation in the proposed architecture. General methods to realize this function needs LUTs, complex multipliers. CORDIC reduces complexity in hardware by usage of simple components like adders, comparators and shifters. output vector, and ui is use to determine the direction of rotation and is given by
[ ( )]
u
i = -sign z i
(4.12) where z(i) is the phase rotated in i-th stage. After finishing the rotation of N stages, the output vector need to be multiplied by the factor1 2 2
to maintain the same amplitude as input vector. The CORDIC cell structure of i-th stage is illustrated as Fig. 4.6.
-Sign[z(i)]
+/--Sign[z(i)]
+/--Sign[z(i)]
+/-y(i+1) x(i+1) x(i)
y(i)
tan-1(2-i)
>> i
>> i
θi
θi+1
Figure 4.6 The architecture of CORDIC cell at i-th stage
The overall architecture of CORDIC is shown as Fig. 4.7
Figure 4.7 The architecture of CORDIC module
While implementing CORDIC, there are issues should be considered. The phase range of the input angle should be between -π ~ π , or errors will occur. Another issue is that the angle value between -π ~ π is hard to be expressed in 2’s complement form.
Also, the angular adder can not be implemented by conventional adder and should be redesign. In the proposed design, the input angle of CORDIC is normalized with the factor 2/π, so the range of the phase will be normalized from -2 to 2.
The angle after normalizing is as shown in Fig. 4.8. It shows that the phases can be easily represented as 2’s complement form. The most important of all, overflow
issue can be completely solved in this method. For example, the conventional calculation result of π/2 + 3π/4 = 5π/4 ( = -3π/4), the proposed calculation result obtains result of 01.0(2) + 01.1(2) = 10.1(2) correctly.
00.0(2) 00.1(2)
01.0(2) 01.1(2)
10.0(2)
11.1(2)
11.0(2)
10.1(2)
Figure 4.8 The normalized angle