System Performance

24.4

Required SNR, Ideal 21

33.5 25

Required SNR, PLL Based [2] 23

130

Required SNR, This Work 21.8

33.3 24.4

Required SNR, Ideal 21

33.5 25

Required SNR, PLL Based [2] 23

130

Higher performance can be obtained in the proposed baseband receiver because the effects of CFO are outstandingly suppressed by the proposed CFO mitigation and adaptive PET.

The PER curves of different transmission modes for STBC-MIMO (2x2 system) are shown in Fig. 3.5. System constraint for 802.11a and the required SNR to meet 10% PER for STBC-MIMO for 802.11n are listed in Table 3.2. We note that much better performance can be obtained compared with legacy SISO systems due to space diversity of an additional antenna. Especially in low SNR region, outstanding performance can be achieved, thus suitable for low data rate and high performance transmission.

PER

Figure 3.5 PER performance on STBC mode under TGn channel model D, 40ppm CFO and 40 ppm SCO

Table 3.2 System constraint for 802.11a and the required SNR to meet 10% PER for STBC-MIMO for 802.11n

802.11a STBC-MIMO for 802.11n

Data Rate System Constraint

(dB) Data Rate Required SNR

(dB)

6 9.7 6.5 3

9 10.7 13 6

12 12.7 19.5 8

18 14.7 26 10

24 17.7 39 14

36 21.7 52 18

48 25.7 58.5 20

54 26.7 65 21

Chapter 4

Hardware Implementation

In chapter 2, we proposed a tri-mode equalizer for OFDM-based wireless LAN.

Considering hardware implementation efficiently for tri-mode equalizer design, many shared-architectures based on common algorithms and different working timing are derived and utilized in this chapter.

4.1 Common Architecture Design for Tri-mode Equalizer

We proposed a common architecture design for tri-mode equalizer as shown in Fig. 4.1. We note that a Coordinate Rotation Digital Computer (CORDIC) is used to compensate phase errors in our equalizer design. CORDIC is a well-known iterative method for the computation of vector rotation. Compared to Look-up-tables (LUTs), CORDIC reduces the complexity by using adders, shifters, and comparators.

CORDI FFT DeMUX _Mitigation^CFO C

Channel Estimatio

PET n

MUX DeMUX _Detection^MIMO

to Demapping

H RAM Tri-mode

Equalizer

Control

Figure 4.1 Tri-mode equalizer architecture

The signals after FFT will go in CFO mitigation first for SDM-MIMO and STBC-MIMO modes or will bypass it for SISO mode, and then the estimated residual CFO in HT-LTFs will be compensated by CORDIC. The High-Throughput Long Training Fields (HT-LTFs) are used to estimate MIMO channels for SDM-MIMO/STBC-MIMO modes and Legacy Long Training Field (LLF) is used to estimate channel for SISO mode. The estimated channels then will be saved in RAMs.

With estimated channels, PET can track the phase errors caused by residual CFO and SCO. Then send to CORDIC in the same manner to compensate phase errors in data portion. Here we notice that one CORDIC can be fully utilized for two times because CFO mitigation and PET work at different timings. Finally, the data after CORDIC will be equalized by MIMO detection. In the following section, the modules in tri-mode equalizer will be described in detail.

4.2 Modules Design

4.2.1 CFO Mitigation Module Design

The proposed architecture of CFO mitigation is shown as Fig. 4.2.

CFO Mitigation

7 ...

Stream1 pilot 0 ( )*

7 ...

Stream2 pilot 0 ( )*

η D

Á[ ]

Â[ ]

Real Divider

>>

To CORDIC

The proposed CFO algorithm has the main advantage of low complexity as mention in chapter 2. To further reduce the area consumptions, we note a feature that CFO mitigation operates during receiving preambles and PET and MIMO detection work during receiving data portion. For this reason, all the main components i.e. the two marked complex multipliers and the real divider shown in Fig.4.2 can share the hardware resources with MIMO detection and PET respectively, so it achieves very low complexity in hardware.

4.2.2 Channel Estimation Module Design

Fig. 4.3 shows the architecture of the proposed tri-mode channel estimation.

l

Figure 4.3 Tri-mode architecture of channel estimator

The algorithms of channel estimation were introduced in chapter 2. We observe

that the operation in Equation (2.9) can be totally included in Equation (2.13) so shared architectures of channel estimation is used for three modes. The estimated channel frequency response (CFR) is then sent to a smoothing FIR filter with three taps [0.25 0.5 0.25] for SISO mode, or is saved to RAM without smoothing for SDM-MIMO and STBC-MIMO modes on the other hand.

4.2.3 Phase Error Tracking Module Design

The proposed architecture of CFO tracking is shown as Fig. 4.4. Same as the steps of the proposed algorithm mentioned in chapter 2, we divide the architecture to three portions, i.e. pilot pre-compensation, phase estimation and recursive adjustment.

In the pilot pre-compensation portion, the phases of pilots in both data streams are compensated using CORDIC modules. After pilot pre-compensation, the detected pilot phase is the difference between two adjacent OFDM symbols. In the phase estimation portion, the architectures of the weighted average phase estimation for SISO mode and the mean average phase estimation for SDM-MIMO/STBC-MIMO modes are combined together. In addition to mean average phase estimation, there are only two de-multiplexers are addition to the proposed architecture. Most of the components are shared, so this architecture increases little complexity in hardware.

Finally, in the recursive adjustment, error vector at current symbol is calculated and the estimated residual CFO is updated. Using the relationship mentioned in equation (2.26), the estimate of SCO can be obtained from CFO. Then the total phase error is sent back to pilot pre-compensation for next symbol duration and is sent to CORDIC modules outside to correct phase errors in data potion.

,1,mrpYl+ 1,ˆ ,2,mkj mrkYelf l+-- +

,2,mrpYl+

[]Á [] Â

0m ml+

1,ˆmklf

+-1,ˆ ,1,

mkj mrkYelf l+-- + ˆmla+ ˆ mlf+1ˆmla+-

mlf+1ˆmla+-ml+Q

,1,ˆmkul+ ,2,ˆmkul+

ˆ mul+ mla+¢

1

tan

- 2

d

ˆ

ml

a

+

Figure 4.4 The proposed Tri-mode CFO tracker architecture

4.2.4 MIMO Detection Module Design

The channel matrix coefficients of the k-th subcarrier are given by:

1, 3, Equation (4.1) can be re-written as:

1 3 From Equation (2.37), the MMSE filter for SDM-MIMO is:

1 1

We can re-write Equation (4.3) as

* * * * * * * * * * where a is the reciprocal of SNR per receiver, and we ignore the effect of

a

²

because it is relatively small. The output after MMSE filter can be written as ˆ ( ) ^H ( )

X k

=

G Y k

× (4.6) In SISO mode transmission, all the channel frequency responses of h2, h3 and h4 are zeros. We observe Equation (4.5) can be simplified as zero forcing for SISO mode

1

ˆ ( ) Y k( )

X k

=

h

(4.7) On the other hand, STBC detection for STBC-MIMO can be expressed as

0 0

The output of STBC detection can be written as

0 0

From above derivation, we can find some similarity between MMSE detection and STBC detection. Both detections need channel coefficients

h

₁²+

h

₂ ²+

h

₃²+

h

₄ ², and 2x2 matrix multiplications are required. From above observations, the proposed tri-mode MIMO detection is shown as Fig. 4.5.

Figure 4.5 Tri-mode MIMO Detector architecture

While designing the proposed architecture, we notice that the channel coefficients

2 2 2 2

1 2 3 4

h

+

h

+

h

+

h

and matrix multiplier can be shared in hardware. The coefficients which MMSE and STBC need are calculated first at the beginning, and then are sent to divider and matrix multipliers. The incoming data are first divided by g as given in Equation (4.5), and then pass through matrix multiplier for SISO and SDM-MIMO modes. In STBC-MIMO mode, some additional operations are need

while receiving. Data is encoded across symbols so a delay line is needed to save data of last symbol. An extra matrix multiplier and an adder are also needed for 2x2 STBC operations in ML MIMO detection. To further reduce the complexity in hardware, we note that there is only one operation in MMSE/STBC coefficients calculation during a packet length so the additional matrix multiplier (lower position in the Fig. 4.5) can share complex multipliers with coefficients calculation block for STBC-MIMO mode.

4.2.5 CORDIC Module Design

CORDIC is used for phase rotation in the proposed architecture. General methods to realize this function needs LUTs, complex multipliers. CORDIC reduces complexity in hardware by usage of simple components like adders, comparators and shifters. output vector, and ui is use to determine the direction of rotation and is given by

[ ( )]

u

i = -

sign z i

(4.12) where z(i) is the phase rotated in i-th stage. After finishing the rotation of N stages, the output vector need to be multiplied by the factor

1 2 2

to maintain the same amplitude as input vector. The CORDIC cell structure of i-th stage is illustrated as Fig. 4.6.

-Sign[z(i)]

+/--Sign[z(i)]

+/--Sign[z(i)]

+/-y(i+1) x(i+1) x(i)

y(i)

tan^-1(2^-i)

>> i

>> i

θi

θi+1

Figure 4.6 The architecture of CORDIC cell at i-th stage

The overall architecture of CORDIC is shown as Fig. 4.7

Figure 4.7 The architecture of CORDIC module

While implementing CORDIC, there are issues should be considered. The phase range of the input angle should be between -π ~ π , or errors will occur. Another issue is that the angle value between -π ~ π is hard to be expressed in 2’s complement form.

Also, the angular adder can not be implemented by conventional adder and should be redesign. In the proposed design, the input angle of CORDIC is normalized with the factor 2/π, so the range of the phase will be normalized from -2 to 2.

The angle after normalizing is as shown in Fig. 4.8. It shows that the phases can be easily represented as 2’s complement form. The most important of all, overflow

issue can be completely solved in this method. For example, the conventional calculation result of π/2 + 3π/4 = 5π/4 ( = -3π/4), the proposed calculation result obtains result of 01.0(2) + 01.1(2) = 10.1(2) correctly.

00.0₍₂₎ 00.1(2)

01.0₍₂₎ 01.1(2)

10.0₍₂₎

11.1(2)

11.0(2)

10.1(2)

Figure 4.8 The normalized angle

4.3 Implementation Results

4.3.1 Fixed-point Simulation

Before developing RTL code, we have to determine the bit numbers of each operation. To reduce hardware complexity, fewer bit numbers are better. However, hardware cost and system performance are trade-off in hardware implementation. The bit numbers of main modules in tri-mode equalizer are listed in Table 4.1.

After the bit numbers of each operation are determined, fixed-point simulation are utilized to evaluate the system performance in hardware. The performance comparison of floating point and fixed point simulations in the highest data rate condition of 64QAM and 5/6 coding rate under TGn channel model D, 40ppm CFO

and 40ppm SCO for 2x2 SDM-MIMO are shown as Fig. 4.9. We can note that in Fig.

4.9, there is only 0.3 dB performance loss in fixed-point simulation compared with floating point simulation.

Table 4.1 Bit numbers of main modules

Module Name Bit Numbers

CFO Mitigation Input 16

Channel Estimation Input 11

PET Input 16

MIMO Detection Input 11

CORDIC Input 13

CORDIC Output 16

22 24 26 28 30 32 34 36 38

10^-2 10^-1 10⁰

The PER Comparison between Floating Point and Fixed Point Simulation

SNR

PER

64QAM, code rate 5/6, Fixed Point 64QAM, code rate 5/6, Float Point PER = 10%

Figure 4.9 Performance comparisons between floating point and fixed point simulation.

4.3.2 Hardware Synthesis

In this section, we discuss the implementation of the proposed tri-mode equalizer design. We use SYNOPSYS Design Compiler to synthesize the register-level verilog file in a UMC 0.18μm cell library with 20MHz clock rate. The Hardware complexity of the tri-mode equalizer is shown in Table 4.2.

Table 4.2 Hardware complexity of the tri-mode equalizer

Main Block Gate Count Memory Size (Bytes)

Mitigation 8k 0

Channel

Estimation 6k 4.5

CORDIC * 2 16k 0

PET 37k 0

MIMO

Detection 116k 2.75

Total 209k 7.25

From Table 4.2, the total gate counts of the tri-mode equalizer are 209k, and it occupies 7.25 Bytes of memory. The proposed tri-mode MIMO detection which occupies highest percentage in area in the tri-mode equalizer is compared with former approaches as listed in Table 4.3.

Table 4.3 Gate count comparison for 2x2 MIMO symbol detectors

Mode Gate Count

[21] SISO 60K

[22] SDM 89K¹

[24] SDM / SFBC 128K

This Work SDM / STBC / SISO 116K

In order to analyze whether the proposed design meets the timing requirement in 802.11n, timing report is shown as:

****************************************

Operating Conditions: slow Library: slow Wire Load Model Mode: top

Startpoint: I_CFO_MITIGATION/counter_reg[5]

(rising edge-triggered flip-flop clocked by clock) Endpoint: COMPENSATE2_CORDIC/out_x_reg[15]

(rising edge-triggered flip-flop clocked by clock) module to CORDIC module. The system timing constraint is 50ns, library setup time is 0.43ns and data required time of critical path is 49.57ns, so timing of the proposed design meets system requirements.

Figure 4.10 The synthesis report of tri-mode equalizer on ISE

Figure 4.12 VeriComm and FPGA board

For FPGA verification, the tri-mode equalizer is also synthesized by XST Synthesizer built in Xilinx ISE, the synthesis report is show as Fig 4.10.

Finally, to verify the functional correctness on FPGA, the comparisons of the simulation results of RTL on nWave and emulation results of FPGA on VeriComm are shown in Fig 4.11. Fig. 4.12 depicts the verifying situation. We claim that their behaviors are correct from Fig 4.11 because the outputs are totally identical as inputting the same patterns.

Chapter 5

Conclusions and Future Works

In this thesis, we proposed a tri-mode equalizer design which can operate in SISO/SDM-MIMO/STBC-MIMO for IEEE 802.11n draft. The architecture of tri-mode equalizer is divided to four portions: CFO mitigation, channel estimation, phase error tracking and MIMO detection. In CFO mitigation, the proposed algorithm increases the accuracy of channel estimation effectively and has low complexity in hardware. Zero Forcing channel estimation for SISO mode can be fully integrated into MIMO channel estimation for SDM-MIMO/STBC-MIMO modes in the proposed architecture, so shared-architecture leads to low area consumption for tri-mode channel estimator. In the proposed PET, a full tracking range can be achieved by the pilot pre-compensation scheme, the performance degradation of conventional pilot-based PET due to few pilot numbers can be improved outstandingly, and shared architectures are also considered in the proposed circuit. Finally, Zero Forcing equalization for SISO mode, MMSE MIMO symbol detection for SDM-MIMO mode and ML MIMO symbol detection for STBC-MIMO mode are implemented with a lot of shared architectures to reduce area consumption in circuit. Simulation results show the proposed tri-mode equalizer achieves a better 1.9~3.8dB gain in SNR for 10%

PER compared with conventional approaches because a total solution of residual CFO are proposed. In hardware implementation, totally 209k gate counts are used for tri-mode equalizer. Low area consumption in the proposed circuit design is achieved by using a lot of shared architectures.

In this thesis, we focus on equalizer design for 2x2 MIMO systems. Using this design concept, a tri-mode inner receiver can also be considered in the future. For higher data rate and higher reliability transmission, a MIMO system with higher antenna dimensions will be certainly applied in the future. Therefore, an MIMO equalizer in the high throughput transmission with more antennas will be needed to further explore in the future.

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Vita

姓名 : 黃俊彥 性別 : 男 籍貫 : 宜蘭縣

生日 : 民國七十三年一月二十四日 地址 :宜蘭市西後街 131 號

學歷 : 國立交通大學電子工程研究所碩士班 95/09~97/06 國立中興大學電機工程學系 91/09~95/06 國立宜蘭高級中學 88/09~91/06

論文題目 : A Tri-mode MIMO Equalizer Design for OFDM Based Wireless LANs

三模MIMO 之無線區域網路等化器設計

在文檔中 三模MIMO之無線區域網路等化器設計 (頁 47-0)