Chapter 1 Introduction
1.6 Motivation
As far as we know, the gate capacitance is inversely proportional to the thickness of the gate dielectrics. That is to say, the thinner gate dielectric will result in the higher peak transconductance (Gm_max). However, the Gm_max of the TFT devices using HfO2 gate dielectrics increases with the HfO2 thickness in our work. This phenomenon is contrary to the knowledge we had before. As a result, it is interesting and worthwhile to find out the main cause of this phenomenon.
Apart from the investigation on the electrical characteristics of the TFTs with different HfO2 thickness, the NBTI stress is also studied to compare the reliability of the TFTs with different thickness of HfO2 layers.
Table 1.1 Variation of electronic parameters and corresponding possible degradation mechanism and the main degraded locations.
interface states → → → → HfO
2/Poly-Si interface tail trap states → → → → grain boundary
G m (transconductance)
interface states → → → → HfO
2/Poly-Si interface intra-grain defect density → → → poly-Si film →
S.S. (subthreshold swing)
charge trapping → → → → gate dielectric fixed charge → → → → gate dielectric
interface states → → → → HfO
2/Poly-Si interface
V th (threshold voltage)
Mainly depending on → → → → distribution Electrical parameters
after stressing
interface states → → → → HfO
2/Poly-Si interface tail trap states → → → → grain boundary
G m (transconductance)
interface states → → → → HfO
2/Poly-Si interface intra-grain defect density → → → poly-Si film →
S.S. (subthreshold swing)
charge trapping → → → → gate dielectric fixed charge → → → → gate dielectric
interface states → → → → HfO
2/Poly-Si interface
V th (threshold voltage)
Mainly depending on → → → → distribution Electrical parameters
after stressing
Fig. 1.1 The schematic plot of the NBTI stress mechanism in the TFTs with SiO2 gate dielectrics [32].
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Chapter 2
Experimental Details and Method of Parameter Extraction
2.1 Device Fabrication
As shown in the Fig 2.1, the fabrication of the device was started by depositing a 50nm-thick un-doped amorphous Si (a-Si) layer at 550℃ by low pressure chemical vapor deposition (LPCVD) on the Silicon substrate which was capped with a 500nm-thick thermal oxide layer. Then the a-Si layer was re-crystallized to poly-silicon channel film by the SPC process at 600℃ for 24hr in a N2 ambient. The source and the drain regions were implanted with boron for p-channel TFTs (15keV at 5x1015cm-2). Then the S/D regions were activated at 600℃ for 24hr annealing in a N2 ambient. After the implantation of S/D regions, a 500nm-thick TEOS oxide was deposited on the poly-Si channel film at 700℃
by the LPCVD system for the device isolation. Then the TEOS oxide film was patterned and then etched to be the field oxide for the active region formation.
For the HfO2-TFTs, the 175Å, 415Å and 745Å-thick HfO2 filmswere deposited by the electron-beam evaporator system at room temperature and the process pressure of 10-5 torr. Then all the samples were annealed in the horizontal furnace with O2 at 400℃ for 0.5hr to improve the quality of the gate dielectrics.
After the patterning of the contact holes, aluminum (Al) was deposited by the electron-beam system at room temperature and 5x10-7base pressure as the gate electrodes and the S/D contact pads. Finally, the TFT devices were finished by the definition of source, drain and gate contact pads. All the fabrication
processes were shown in the Fig. 2.1.
2.2 Measurement
The NBTI tests are performed on 10µmx10µm p-channel TFTs with HfO2 thickness of 175, 415 and 745Å, with source and drain grounded during the stress. The samples are stress at a constant voltage for 1000 seconds. The threshold voltage (VTH) and the transconductance (Gm) are extracted using Id-Vg
sweeps performed during periodic interruptions of the stress. Measurements are performed at various stress voltages and 2 different temperature – Room temperature (RT) and 125°C.
2.3 Method of Parameter Extraction (Determination of Thresholod Voltage)
Threshold voltage Vth is one of the most important electrical parameter of semiconductor. However, the precise threshold voltage of the device is difficult to define. Therefore, several methods have been proposed to extract the Vth of different kinds of devices. In MOSFETs, there are two common methods for the determination of Vth. One of them is the linear extrapolation method with the drain current measured at a drain voltage of 50~100mV to make sure the operation in the linear regime. According to the ideal Id-Vg relation in the linear regime:
)
can be ignored at a low drain current and low drain bias. It is a common practice to find the point of the maximum slope of the Id-Vg curve (Gm_max) and fit aIn this work, Vth is defined by the other method which is different from the above description. We make use of a more simple way which is called constant drain current method. This method is utilized in almost every paper in the TFT field. The Vth derived by this way is close to the Vth obtained from the extrapolation method. Here, the Vth is defined as the point at VDS=∣0.1V∣where the drain current Id=(W/L)*100nA for n and p channel, where the W and L are the channel width and the channel length respectively. In this paper, devices were all measured in the size of W=10µm and L=10µm. Thus the Vth is defined as the gate voltage where the drain current Id=1*10-7 A in all of our discussions.
2.3.1 Determination of subthreshold swing
Subthreshold slope (S.S.) is a typical parameter to describe the gate control ability, which reflects how fast the device can be switched from off state to on state. It is defined by the amount of the gate voltage needed to increase or decrease the drain current by one order of magnitude. The S.S should be independent of gate voltage and drain voltage. However, the S.S. of a device is usually affected by the various degradation effects such as charge sharing, avalanche multiplication and punchthrough effect. The S.S. is usually related to the undesirable and inevitable phenomenon such as series resistance and interface states. In LTPS TFTs, the S.S. is also dependent on the trap state in the grain boundaries. It has been reported that the the S.S is strongly related to the trap states near the mid-gap (deep energy level), which is originated from the dangling bonds [1], besides, the low temperature process of the LTPS-TFTs will result in a poor interface between the gate dielectrics and the channel films.
Briefly speaking, the bulk trap states and interface states will degrade the S.S. of LTPS-TFTs.
The formula of subthreshold slope was defined as :
] 1
2.3.2 Determination of on/off current ratio
On/off drain current ratio is other important parameters of TFT devices. High On/off ratio reflects not only the high on current but a small off current (or
leakage current). In TFTs, the on/off drain current ratio of six orders is required for the applications of AMLCDs.
In this paper, the on current is defined as the point at a fixed drain bias of 0.1V where the drain current is at a maximum of the Id-Vg curve. The off current is defined as the point at a fixed drain bias of 0.1V where the drain current is at a minimum. Therefore, the on/off drain current ratio can be derived by the
2.3.3 Determination of field effect mobility
The field effect mobility (µFE) is usually determined from the maximum value of transconductance (Gm) at a low drain bias. The drain current in the linear region (VDS < VGS-Vth ) can be approximated as the following equations :
where W and L are the channel width and the channel length, respectively；Cox is the gate oxide capacitance per unit area and Vth is the threshold voltage. Thus, the transconductance is given by the differential equation:
DS
Therefore, the field-effect mobility is defined as follows:
2.3.4 Determination of the trap state density
In LTPS-TFTs, the trap state density (Nt), which originates from dangling bonds or strained bonds located in the grain boundaries of poly-Si films. The trap state in the channel region will trap free carriers and result in potential barrier height VB to degrade the carrier transportation like the degradation of the field-effect mobility ( μFE), higher threshold voltage (Vth), subthreshold swing (S.S.) and leakage current. Therefore, the grain boundary trap state density is an important parameter that affects the electrical transport properties significantly of poly-Si films. Therefore, it is necessary to extract the trap state density in the channel film. Many researchers have investigated the electrical characteristics and the carrier transport mechanism in the poly-Si TFTs. Among the lots of grain boundary trap state-extraction method, The trap state density is usually derived by the Lenvinson and Proano method [2][3]. And the method is described as follows:
By modifying the mobility µb and replacing the dopant concentration with gate induced charge density NG, the corrected expression of the transfer characteristics (ID-VG) at low drain voltage in the poly-Si films is very similar with that in the regular MOSFET’s. It is expressed as:
) )
The equation above was modified by Proano et al [3]. It is found that the behavior of the carrier mobility under low gate bias can be expressed more accurately by using the flat-band voltage VFB instead of the threshold voltage (Vth). The flat-band voltage VFB is defined as the gate voltage which corresponds to the minimum drain current. Furthermore, Lenvinson et al. [2] assumed that the channel thickness tch is constant and equal to the thickness of the poly-Si film tpoly-Si. This simplified assumption is acceptable only for the very thin film (tpoly-Si), which is not applicable to the common thickness for the poly-Si TFTs.
As a result, a better approximation for the channel thickness tch in an undoped poly-Si film is given by defining the channel thickness as the thickness at which 80% of the total charge resides. Therefore, by solving the Poisson’ equation, the channel thickness is given by the equation:
)
Substituting the modified terms discussed above for the equation (2.9), thus the drain current ID can be expressed as the following equation:
) )
According to the equation (2.11), we can extract the trap state density (Nt) from the slope of the curve ln[ID/(VG-VFB)]versus (VG-VFB)-2. the effective grain
SiO2
a-Si
(a) Thermal oxidation and an amorphous Si (α-Si) film was deposited by LPCVD.
SiO2
Poly-Si
(b) The α-Si film was crystallized into the poly-Si film by SPC at 600℃ for 24hr.
SiO
2Poly-Si
B
11+B
11+(c) The source and drain regions (S/D) were implanted with boron and then activated at 600℃ for 24hr.
SiO
2Poly-Si
B
11+B
11+(d) TEOS SiO2 was deposited as the field oxide and the active region was defined.
SiO2 Poly-Si
HfO2
B11+ B11+
(e) The HfO2 films with the thickness of 175Å, 415Å and 745Å were deposited by the e-beam evaporator as the gate dielectrics. Post deposition anneal (PDA) was performed at 400℃ in the O2 ambient for the densifying of the HfO2 films.
SiO2 Poly-Si
HfO2
B11+ B11+
(f) S/D Contact holes were defined and opened.
SiO2
Poly-Si HfO2
B11+ B11+
Al
Al Al
(g) Aluminum films were deposition by the e-beam evaporator as gate electrodes and the gate and S/D regions were defined and opened.
SiO
2Poly-Si HfO
2B
11+B
11+Al
Al Al
(h) The HfO2-TFT Devices are sintered at 400℃ for 30 min in a N2 ambient.
Fig. 2.1 The device fabrication of the HfO2-poly-Si TFTs.
Chapter 2
Reference
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Chapter 3
Electrical Characteristics of the p-channel LTPs TFTs with Different Thickness of High-κ Gate Dielectrics
3.1 Electrical Characteristics
In this work, several possible mechanisms that contribute to the degradation or the enhancement of the peak transconductance (Gm_max) are systematically investigated and a new model is firstly proposed to explain the enhanced Gm_max for the TFTs with the thicker HfO2 gate dielectrics.
Fig. 3.1 (a) shows the transfer characteristics (ID-VG) of the poly-Si TFTs with HfO2 gate dielectrics, which had physical thickness of 250, 500, 700, 1000 and 1700Å, respectively. It is surprisingly that the value of the peak
Fig. 3.1 (a) shows the transfer characteristics (ID-VG) of the poly-Si TFTs with HfO2 gate dielectrics, which had physical thickness of 250, 500, 700, 1000 and 1700Å, respectively. It is surprisingly that the value of the peak