Ⅲ-Ⅴ compound semiconductors have the advantages which high electron mobility, high breakdown field, low power consumption and rich band gap engineering [3-5]. Thus they are expected to out-perform silicon-based CMOS applications such as high-speed and low-power consumption devices. GaAs is of great importance for scientific understanding of
Ⅲ-Ⅴ interfaces and GaAs MOS devices can be used as a sensitive test bed for all dielectric techniques. The treatment or passivation techniques developed on GaAs can naturally be applied to InGaAs or other Ⅲ-Ⅴ compound semiconductors [6].
The major challenge in developing Ⅲ-Ⅴ devices is large interface states density ( Dit ) associated with dielectric/Ⅲ-Ⅴ interface reduces the free carrier density available for transport and can lower the effective channel mobility. In the past few years, for the studies of the dielectric/Ⅲ-Ⅴ interface, especially the (In)GaAs substrate, the several studies have been devoted in intensively searching the high interface quality insulators and efficient passivation methods. Except for SiO2 and Si3N4, (Gd,Ga)2O3 [7] and atomic-layer-deposited (ALD) Al2O3
[8], HfO2 [9] high-k dielectrics are of particular interest; meanwhile, the sulfur chemical treatment[10], and Si and Ge [11] as the interfacial passivation layers are currently active approaches to protect the surface of III-V semiconductors prior to the dielectric deposition.
3
1.3 Organization of The Thesis
In Chapter 2, we exhibited the common electrical characteristics of MOS capacitors on GaAs substrate and calculated surface potential fluctuation. We also introduced the conductance methods to extract Dit distributions within energy bandgap to compare high-low frequency method.
In Chapter 3, we studied the reduction of native oxides on GaAs substrates before ALD of Al2O3. After trimethylaluminum (TMA) pluses, it is to suppress native oxides on GaAs surface. Subsequently, we deposited ALD-Al2O3 as gate dielectric to fabricate MOS capacitors and examined the impact of interface quality on the electrical characteristics; the capacitance-voltage (C−V) characteristics were studied. Besides, we also investigated the electrical properties on the different surface orientation of GaAs substrates. Two different GaAs substrates, p-type (111)A and p-type (100), were also fabricated MOS capacitors and studied the impact of the different surface orientation on the electrical characteristics.
In Chapter 4, we utilized the results in optimization of Al2O3/GaAs interface to fabricate the enhance-mode GaAs n-MOSFET on semi-insulating GaAs substrate and also fabricated MESFET on InGaAs structures grown by molecular beam epitaxy (MBE). We discussed their Id-Vg and Id-Vd electrical characteristics and determined the electronic mobility, source/drain resistance.
In Chapter 5, finally, we summarized the experimental results in the thesis and gave the conclusion and suggestions for future work.
4
[2] J. Robertsona, B. Falabretti, “Band offsets of high K gate oxides on III-V semiconductor,”
J. Appl. Phys., vol. 100, p. 014111, 2006.
[3] K. Iiyama, Y. Kita, Y. Ohta, M. Nasuno, S. Takamiya, K. Higashimine, and N. Ohtsuka, IEEE Trans. Electron Devices, vol. 49, p. 1856, 2002.
[4] J. K. Yang, M. G. Kang, and H. H. Park, J. Appl. Phys. vol. 96, p. 4811, 2004.
[5] P. D. Ye, G. D. Wilk, J. Kwo, B. Yang, H. J. L. Gossmann, M. Frei, S. N. G. Chu, J.
P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, IEEE Electron Device Lett., vol. 24, p. 209, 2003.
[6] M. Xu, Y. Q. Wu, O. Koybasi, T. Shen, and P. D. Ye, “Metal-oxide-semiconductor field-effect transistors on GaAs (111)A surface with atomic-layer-deposited Al2O3 as gate dielectrics,” Appl. Phys. Lett., vol. 94, p. 212104, 2009.
[7] B. Yang, P. D. Ye, J. Kwo, M. R. Frei, H. J. L. Gossnann, J. P. Mannaerts, M. Sergent , M. Hong, K. Ng, and J. Bude, J. Cryst. Growth, vol. 251, p. 837, 2003.
[8] H.-L. Lu, L. Sun, S.-J. Ding, M. Xu, D. W. Zhang, and L.-K. Wang, “Characterization of atomic-layer-deposited Al2O3/GaAs interface improved by NH3 plasma pretreatment,”
Appl. Phys. Lett., vol. 89, p. 152910, 2006.
[9] M. Zhu, C.-H. Tung, and Y.-C. Yeo, “Aluminum oxynitride interfacial passivation layer for high-permittivity gate dielectric stack on gallium arsenide,” Appl. Phys. Lett. vol. 89,
5
p. 202903, 2006.
[10] M.-K. Lee, C.-F. Yen, J.-J. Huang, and S.-H. Lin, “Electrical characteristics of postmetallization-annealed MOCVD-TiO2 films on ammonium sulfide-treated GaAs,”
J. Electrochem. Soc., vol. 153, p. F266, 2006.
[11] H.-S. Kim, I. Ok. M. Zhang, T. Lee, F. Zhu, L. Yu, and J. C. Lee, “Metal gate-HfO2
metal-oxide-semiconductor capacitors on n-GaAs substrate with silicon/germanium interfacial passivation layers,” Appl. Phys. Lett., vol. 89, p. 222903, 2006.
6
Fig. 1.1 Transistor scaling and research roadmap demonstrated by R. Chau, Intel Corp.
7
Fig. 1.2 One of the several possible future high-performance CMOS architecture by D.
Lin, IMEC.
8
Chapter 2
Electrical characteristics of GaAs MOS capacitor with Al 2 O 3 gate
dielectric
2.1. Introduction
Electrical characteristics, such that capacitance-voltage (C-V) and conductance-voltage characteristics (G-V), are regularly used in research and development to understand important parameters of metal-oxide-semiconductor (MOS) capacitor which are like the flatband voltage (VFB), fixed charge (Qf), effective oxide thickness (EOT) and the quality of dielectric/Ⅲ-Ⅴ interface. The C-V and G-V characteristics are the methods of choice to extensively study the interfacial characteristics because of the inherent sensitivity of the electrical measurements and the ease-of-use of the involved methods.
Interfacial characteristic is a crucial challenge for realizing Ⅲ-Ⅴ MOS capacitor.
Therefore, it is essential that the quality of interface is evaluated correctly. For example, poor interfacial quality can cause major distortions of the electrical characteristics and result in extensive misconstruction in the interface states density (Dit) or other perfunctory parameters extracted from these measurements. The energy bandgap of III-V materials also affect the conductance characteristics in several ways that do not have to be considered in Si-based devices. The correct interpretation of the used electrical characteristics therefore becomes of
9
paramount importance in III-V technology.
Thorough understanding of the electrical characteristics will give the proper extraction of the MOS capacitor parameters and of the Dit distribution within the energy bandgap. In this chapter, the understanding of the behavior of GaAs MOS capacitor with the Dit contribution is provided based on firmly established Si/SiO2 MOS capacitor theory [1-4].
The conductance method, proposed by Nicollian Goetzberger in 1967, is one of the most sensitive methods to determine Dit [3]. Dit of 109 cm-2eV-1 and lower can be measured. It is also the most complete method, because it yields Dit in the depletion and weak inversion portion of the bandgap, the capture cross-sections for majority carriers, and information about surface potential fluctuation. The technique is based on measuring the equivalent parallel conductance Gp of an MOS capacitor as a function of bias voltage and frequency. The conductance, representing the loss mechanism due to interface traps capture and emission of carriers, is a measure of the interface trap density.
Fig.2.1(a) illustrates the simplified equivalent circuit of MOS capacitor appropriate for the conductance method. It consists of the oxide capacitance Cox, the semiconductor capacitance Cs, and the interface state capacitance Cit. The capture-emission of carriers by Dit is a losing process, represented by the resistance Rit. It is convenient to replace the circuit of Fig. 2.1(a) by Fig. 2.1(b), where Cp and Gp are given by
10
Interface state at the dielectric/substrate interface, however, are continuously distributed in energy throughout the energy bandgap. Capture and emission occurs primarily by interface state located within a few kT/q nearby the Fermi level, leading to a time constant dispersion and giving the normalized conductance as
Gp qDit Capacitance meters generally assume the device to consist of the parallel Cm-Gm combination in Fig. 2.1(c). A circuit comparison of Fig. 2.1(b) to Fig. 2.1(c) gives Gp/ in term of the measured capacitance Cm, the oxide capacitance, and the measured conductance Gm as
Gp
GmCox2
Gm2 2 Cox Cm 2 2.6 In the addition, the device has series resistance which has so far been neglected. Series resistance is a common parasitic affecting C-V and G-V measurement of MOS capacitor. The series resistance is due to the resistance of the bulk semiconductor material and/or the gate electrode material, as well as the contact resistances.The more complete circuit is shown in Fig. 2.1(d) and Gt represents the tunnel conductance and rs represents the series resistance.
11 Cm and Gm are the measured capacitance and conductance. The series resistance is determined by biasing the MOS capacitor into accumulation according to [6]
rs Gma
Gma2 2Cma2 where Gma and Cma are the measured conductance and capacitance in accumulation.
From Eq.(2.3), we assumed the capture cross section = 1×10-15 cm2 and plotted the characteristic emission frequencies of trapped charge carriers in GaAs at the different temperature as a function of the position of the trap in the energy bandgap, as presented in Fig.
2.2. In order to get a good continuous distribution of Dit , we have to measure C-V curve with multi- frequency at the different temperature.
2.2 Sample Preparation
oxide on the surface of substrate at 350 °C for 10 min and then the Al2O3 gate dielectric was deposited by atonic-layer-deposition (ALD) at 250 ℃, followed by post deposition annealing (PDA) at 600 °C for 15 s in a N2 ambient. Thermal evaporated 400 nm Al was patterned as gate electrodes through the lithography. Finally, Ti/Pt/Au ( 5 nm/30 nm/180 nm ) was12
deposited by e-beam evaporator as backside contact. The complete process flow was shown in Fig. 2.3. The electrical characteristics of Al/Al2O3/p-GaAs/TiPtAu MOS capacitors were measured using an HP4284 and HP4200, respectively.
2.3 Results and Discussion
2.3.1 Multi-Frequency C-V of GaAs MOS Capacitor
In the beginning, exhibiting the basic properties of the GaAs MOS capacitor, C-V curves, include different measurement temperatures at 25℃ and 125℃, as shown in Fig. 2.4 (a) and (b), respectively. The frequency and temperature dependent C-V characteristic was observed obviously because of Dit contribution which is distributed within the energy bandgap [6]. Besides, the quasi-static C-V was also shown in Fig. 2.5 and calculating the surface potential, ϕs, is a function of gate voltage. Berglund proposed [7]
ϕs 1 CQSCV Cox
VG2 VG1
dVG
where CQSCV is the quasi-static C-V curve as a function of gate voltage. Integration from VG1
= VFB makes △ = 0, because band bending is zero at faltband. Integration from VFB to accumulation and from VFB to inversion gives the surface potential across the energy bandgap range. Fig. 2.6 illustrates the calculated result, surface potential versus gate voltage ( ϕs-VG ).
Utilizing high-frequency C-V curve and quasi-static C-V to extract Dit as a function of gate voltage by high-low frequency method is described in Eq. (2.12) [8].
Dit Cox where the value of Cox is defined on accumulation of quasi-static C-V. After Dit extraction by high-low frequency method and x-axis conversion by surface potential as function of gate
13
voltage, result in Dit distribution within energy bandgap was displayed in Fig. 2.7.
2.3.2 Conductance Method Application of GaAs MOS Capacitor
Calculating the series resistance by Eq. (2.10) after measurement at 25℃. The result of series resistance extraction was shown in Fig. 2.8, and fitting the series resistance value, rs = 122 Ω. Next, correction of Cc and Gc by Eq. (2.8) and Eq. (2.9), respectively, and the plotting the Gp/ versus frequency by using Eq. (2.7). Fig. 2.9 (a) and (b) displayed Gp/ as a function of frequency through the correction of series resistance and calculation by conductance method. As same as before, plotting the Gp/ as a function of frequency curve which data was measured at 125℃ and the result was shown in Fig. 2.9 (c) and (d). Finally, getting the peak of Gp/ -frequency curve and determining the Dit by using Eq. (2.5). Fig.
2.10 illustrates the Dit distribution within energy bandgap as derived from measurement on GaAs MOS capacitor with ALD-Al2O3 gate dielectric.
2.3.3 Comparison of D
itExtraction
Fig. 2.11 presented the comparison of Dit extraction between high-low frequency method and conductance method on GaAs MOS capacitor with ALD-Al2O3 gate dielectric, and two Dit distributions from the different extraction methods have the same trends which indicate that the high value of Dit was close to mid-gap. The value of Dit from high-low frequency method is overestimated due to some detail; it may be the series resistance effect which has been neglected. Moreover, for high-frequency curve of high-low frequency method, the measurement must be sufficiently high to interface states do not respond, but for MOS capacitors with high Dit there will be some response due to interface traps. The conductance
14
method have the simplified but plentiful circuit model, combining multi-frequency C-V and elevated-temperature measurement enhance the sensitivity near mid-gap allowing the detection of trap energy levels [9].
2.4 Summary
After fabricating a MOS capacitor on GaAs substrates, we could have a standard operation process to extract the electrical characteristic of GaAs MOS capacitors with ALD-Al2O3 gate dielectric. At the first, we measured quasi-static C-V and the multi-frequencies of C-V at the different temperature conditions. Next, we calculated the surface potential as a function of gate voltage by Berglund’s integration. We can realize the fluctuation of Fermi level (EF) on the surface of GaAs substrate, and judge it weather reaches the inversion portion of the band gap or not. After Dit extraction by conductance method, we can accurately determine Dit distribution across the energy bandgap. Finally, utilizing the electrical characteristics of the GaAs MOS capacitor to decide the experimental condition is suitable in manufacture procedure of enhance-mode GaAs n-MOSFET.
15
Reference
[1] C.G.B. Garrett and W.H. Brattain. Physical theory of semiconductor surfaces. Physical Review, vol. 99, p. 376-387, 1956.
[2] K. Lehovec. Frequency dependence of the impedance of distributed surface states in MOS structures. Appl. Phys. Lett., vol. 8, p. 48, 1966.
[3] E.H. Nicollian and A. Goetzberger. The Si/SiO2 interface - electrical properties as determined by the metal-insulator-silicon conductance technique. Bell Syst. Tech. J., vol. 46, p. 1055, December 1967.
[4] Nicollian and Brews. MOS (Metal Oxide Semiconductor) Physics and Technol-ogy., Wiley & Sons, New York, 1982.
[5] E.M. Vogel, W.K. Henson, C.A. Richter, and J.S. Suehle, “Limitation of Conductance to the Measurement of the Interface State Density of MOS Capacitors with Tunneling Gate Dielectrics,” IEEE Trans. Electron Dev., vol. 47, p. 601-608, March 2000; T.P. Ma and R.C.Barker, “Surface-State Spectra from Thick-oxide MOS Tunnel Junctions,”
Solid-State Electron. vol. 17, p. 913-929, Sept. 1974.
[6] G. Brammertz, H. C. Lin, K. Martens, D. Mercier, C. Merckling, J. Penaud,c C.
Adelmann, S. Sioncke, W. E. Wang, M. Caymax, M. Meuris, and M. Heyns,
“Capacitance–Voltage characterization of GaAs–Oxide Interfaces,” Journal of The Electrochemical Society, vol.155, p. 945-950, 2008.
[7] C.N. Berglund, “Surface States at Steam-Grown Silicon-Silicon Dioxide Interfaces,” IEEE Trans. Electron Dev., vol. 13, p. 701-703, Oct. 1966.
[8] R. Castagne and A. Vapaille, “Description of the SiO2-Si Interface Properties by Means of Very Low Frequency MOS Capacitance Measurements,“ Surf. Sci., vol. 28, p. 157-193, Nov. 1971.
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[9] E. Duval and E. Lheurette, “Characterization of Charge Trapping at the Si-SiO2 (100) Interface Using high temperature Conductance Spectroscopy,” Microelectron. Eng., vol.65, p. 103-112, Jan. 2003.
17
Trap energy within bandgap ( eV )
25oC
18
Fig. 2.3 The structure and process flow of Al/Al2O3/p-GaAs (100)/TiPtAu MOS capacitor.
Surface cleaning by HCl+ NH4OH+ (NH4)2S
Thermal desorption at 350℃ for 30min
ALD-Al2O3 deposition at 250 °C
PDA (600℃, 15s in N2)
400nm Al gate electrode
Au/Pt/Ti backside contact
19
-3 -2 -1 0 1 2
20 40 60 80
100 Measurement at 25oC
Capacitance, C ( pF )
Gate voltage, VG ( volt ) (a)
-3 -2 -1 0 1 2
20 40 60 80
100 Measurement at 125oC
Capacitance, C ( pF )
Gate voltage, VG ( volt ) (b)
Fig. 2.4 Multi-frequency C-V curve of Al/Al2O3/p-GaAs (100)/TiPtAu MOS capacitor at (a) 25℃, (b) 125℃measurement condition.
20
21
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1E12
1E13 1E14 EV
D it ( 1/eVcm2 )
Surface potential, s ( eV )
EC
Fig. 2.7 Dit distribution by high-low frequency method of Al/Al2O3/p-GaAs (100)/TiPtAu MOS capacitor.
0.0 200.0k 400.0k 600.0k 800.0k 1.0M 0
200 400 600 800 1000
Series resistance, r s ( ohms )
Frequency, f ( Hz )
rs = 122
Fig. 2.8 Series resistance extraction of Al/Al2O3/p-GaAs (100)/TiPtAu MOS capacitor.
22
Fig. 2.9 Gp/ as a function of frequency (a) and (b) at 25℃ measurement condition; (c) and (d) at 125℃ measurement condition.
100 1k 10k 100k
23
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
1E11 1E12 1E13
EC
D it ( 1/eV cm2 )
Energy in bandgap (eV)
25oC 125oC
EV
Fig. 2.10 Dit distribution by conductance methods of Al/Al2O3/p-GaAs (100)/TiPtAu MOS capacitor.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
1E11 1E12 1E13 1E14
EV Energy in bandgap (eV)
High-low frequency method Conductance method
EC
D it ( 1/eV cm2 )
Fig. 2.11 Comparison of Dit extractions by high-low frequency method and conductance
24
Chapter 3
Optimization of Al 2 O 3 /GaAs interface with MOS capacitor
3.1 Introduction
Today, in the semiconductor industry, Ⅲ-Ⅴ compound materials are used widely in such applications as optoelectronic devices, photodiodes, high-electron-mobility transistors (HEMTs), and other high-frequency devices. In order to obtain high-speed and low-power
Ⅲ-Ⅴ metal-oxide-semiconductor (MOS) logic devices, a high quality interface between insulator and Ⅲ-Ⅴ is imperative. A large interface states density (Dit) within the Ⅲ-Ⅴ energy bandgap was caused by the native surface oxides is identified as a serious device challenge for Ⅲ-Ⅴ based devices [1-2]. Studies into competitive insulators on Ⅲ-Ⅴ compound semiconductors and efficient passivation methods have been performed for more than four decades; the poor quality of the insulator/substrate interface has been the prime obstacle hindering the realization of III-V MOS devices.
As mentioned in the chapter 1, GaAs is of great importance for scientific understanding of Ⅲ-Ⅴ compound material interfaces and GaAs MOS devices can be used as a sensitive test bed for all dielectric techniques. The treatment before insulator deposition or passivation layers between insulator and substrate techniques are developed on GaAs can naturally be applied to (In)GaAs or other Ⅲ-Ⅴ compound semiconductors [3]. Excluding SiO2 and Si3N4 ,
25
(Gd,Ga)2O3 , and HfO2 high-k dielectrics are also potential candidates for use on Ⅲ-Ⅴ compound substrates. One route of obtaining a native oxide-free interface that has attracted the attention of researchers is the “self-cleaning” [4-7]; in which the native oxides on GaAs get a reduction during the atomic layer deposition (ALD) of HfO2 or Al2O3 due to ALD precursor chemistry, tetrakis(ethylmethylamino)hafnium (TEMAH, Hf[N(C2H5)(CH3)]4) and trimethylaluminum (TMA, Al(CH3)3), separately. The self-cleaning during the ALD and the using of ultra-thin Si or Ge interfacial passivation layers are both practical techniques for improving the interface between insulator and Ⅲ-Ⅴ compound material. The pretreatment on GaAs by the ALD precursor prior to deposition of the gate dielectric has been reviewed comprehensively; the improvement in the device performance depends strongly on the ALD precursor pretreatment procedure. The in situ or ex situ deposition of several Si or Ge monolayers on GaAs can reduce the Dit to ca. 1×1010 –1×1011 cm-2 eV-1 [8-9]; this passivation technique has received renewed interest in recent years. Besides, the different crystalline surfaces of GaAs substrates were found that a much higher driving current on GaAs(111)A n-metal-oxide-semiconductor field-effect transistor (MOSFET). This experimental result conclusively demonstrated that Fermi-level (EF) pinning is not an intrinsic property of GaAs, but is orientation dependent [10].
Subsequent thermal annealing can further improve the quality of insulator films deposited on GaAs [11]. Meanwhile, during high temperature processing it is important to inhibit the loss of As within the GaAs substrate and also suppress the formation and subsequent incorporation of native oxides; these processes lead directly to electrical deterioration in GaAs MOS capacitors [12]. The impact of rapid thermal annealing ( RTA ) on the properties of various high-k/GaAs structures has been studied previously [13].
However, the correlations between these thermal reactions and the MOS performance have not been established in detail. In this study, we examined the electrical characteristics of
26
ALD-Al2O3 thin films deposited on an ALD precursor treated GaAs surface and then monitored the impact of postdeposition annealing (PDA) process. ALD is an ultrathin film deposition technique based on sequences of self-limiting surface reactions, which enables thickness control on the atomic scale. Unlike CVD, there is less need of reactant flux homogeneity, which gives large area capability, excellent conformality and reproducibility.
Other advantages of ALD are the wide range of film materials available and high density.
Also, lower deposition temperature can be used in order not to affect sensitive substrates.
The deposition mechanism of ALD is like chemical vapor deposition (CVD). We introduce the unique feature of the step-by-step deposition in ALD by using a general example of Al2O3 film deposition. It is well known that Al2O3 films can be grown by using alternating pulses of Al(CH3)3 (TMA, the aluminum precursor) and H2O (the oxygen precursor) in the presence of N2 carrier gas flow. Its mechanism procedures for one deposition cycle are illustrated in Fig. 3.1. At first, TMA is fed into the reactor and react with the OH bond on the GaAs substrate. Second, the reactor is purged with pure N2 gas to clean out residual TMA. Third, H2O is purged into the reactor and forms Al2O3 on surface. Finally, the reactor is purged with pure N2 gas again to clean out residual H2O.
3.2 Experimental Procedures
MOS capacitor structures were fabricated on high Si-doped ( p-type, ~ 5×1017 cm-3 ) GaAs substrates. At first, the sample was rinsed in the diluted HCl ( HCl : H2O = 1 : 3 ) solution for 3 min, followed by rinsed in deionized (D.I.) water for 5 min. Second, the sample was rinsed in the diluted NH4OH ( NH4OH : H2O = 1 : 10 ) solution for 10 min, followed by rinsed in D.I. water for 5 min. Third, the sample was rinsed in the (NH4)2S solution for 10 min, followed by rinsed in D.I. water for 5 min. After surface cleaning, the sample was loading
27
into the ALD chamber, followed by surface pretreatment with TMA 20 cycles pulse at 250
℃. Next, the Al2O3 gate dielectric was deposited at 250 ℃, followed by PDA at 600 °C for 15 s in an N2 ambient. Thermal evaporated 400 nm Al was patterned as gate electrodes through the lithography. Finally, Ti/Pt/Au ( 5 nm/30 nm/180 nm ) was deposited by e-beam
℃. Next, the Al2O3 gate dielectric was deposited at 250 ℃, followed by PDA at 600 °C for 15 s in an N2 ambient. Thermal evaporated 400 nm Al was patterned as gate electrodes through the lithography. Finally, Ti/Pt/Au ( 5 nm/30 nm/180 nm ) was deposited by e-beam