Chapter 1 Introduction
1.2 Motivation
The rapid advance of integrated circuit technology has moved the minimum feature size into nanometer region. The vertical dimension also needs to be shrunk so as to improve the characteristics of device. Thus, reducing the junction depth becomes critical for advanced CMOS devices.
Shallow junctions are hard to achieve because the ion implantation process will produce the implanted dopant profile to a given depth.
Furthermore, the lateral spreading resistance and contact resistance of a shallow junction are often too large. [11]; as a result, the speed of device may be slowed down by the parasitic resistance. This problem can be alleviated by metallizing the source/drain junction with silicide. However, the quarter-micron device requires a junction depth of less than 0.1 µm and the silicidation of such a shallow source/drain junction will consume a good part of the high doping regions. The major obstacle for the silicidation of ultra shallow junctions comes from the nonuniform
silicide/silicon interface which may lead to local spiking of the junction.
Consequently, the junction leakage may increase enormously after the silicidation process. To avoid this problem, the silicide film must be much thinner than the junction depth.
In this thesis, we want to investigate the activation of B and P implant through silicide (ITS). We clarified the thermal budge required for deactivation of B/P and also showed the impact of this phenomenon on achieving a shallow junction with a low sheet resistance.
1.3 Organization of the Thesis
In this thesis, we concentrate our efforts on the activation of B and P implant through silicide by RTA process. In chapter 1, brief introduction metal-silicide technology history evolution. In chapter 2, first overview of metal-silicide technology is given to describe the various applications and process technologies. Second the process flow of fabrication will be described.
In chapter 3, the detail discussion of characteristics includes physical properties, electrical properties, current transport mechanism, doping profile extraction and temperature effect. In chapter 4 is conclusions and chapter 5 is future works.
1.4 References
[1] Anne Lauwers, An Steegen Muriel de Potter, Richard Lindsay, Alessandra Satta, Hugo Bender, and K. Maex, American Vacuum Society B 19(6) (2001).
[2] J.B. Lasky, J. S. Nakos, O. J. Cain, and P. J. Geiss, IEEE Trans, Electron Device 38, 262 (1991).
[3] K. Maex, Mater. Sci, Eng. R11, 53 (1993).
[4] A. E. Morgan, E. K. Broadbent, M. Delfino, B. Coulman, and D. K.
Sadana, J. Electrochem. Soc. ,vol.134, no. 4, p. 925 (1987).
[5] Q. F. Wang, K. Maex, S. Kubicek, R .Jonckheere, B. Kerkwijk, and R.
Verbeeck, VLSI Tech. Dig. Tech. Paper, p. 17 (1995).
[6] B. S. Chen, and M. C. Chen, “Formation of Cobalt silicided Shallow Junction Using Implant Into/Through Silicate Technology and Low Temperature Furnace Annealing,” IEEE Trans.Electron Devices, vol. 43, no. 2, pp. 258-266, Feb. (1996).
[7] K. Goto, J. Watanabe, T. Sukegawa, A. Fushida, T. Sakuma, and T.
Sugii, “A Comparative Study of Leakage Mechanism of Co and Ni Salicide Processes,” IEEE Annual International eliability Physics Symposium, pp. 363-369, (1998).
[8] A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, Symposium on
VLSI Technology Digest of Technical Papers, 9A-3, (2005).
[9] T. Ohguro, T. Morimoto, Y. Ushiku, and H. lwai,“Analysis of enormously large junction leakage current in nickel-silicided n-type diffused layers and its improvement,”in Ext. Abst. SSDM, p. 192, (1993).
[10] T. Ohguro, S. Nakamura, E. Morifuji, M. Ono, T. Yoshitomi, M.
Saito, H. S. Momose, and H. Iwai,“Nitrogen-doped nickel monosilicide technology for deep submicron CMOS salicide,”in IEDM Tech. Dig., p.
453, (1995).
[11] K. K. Ng, and W. T. Lynch, “The impact of intrinsic series resistance on MOSFET scaling,”IEEE Trans. Electron Device, vol. 34, p. 503, (1987).
Chapter 2
Formation and Characterization of Boron/Phosphorous Implanted Through Silicide by Subsequence Thermal Process
2.1 Introduction
As device dimension is scaled down to deep submicron, not only the size of gate electrode is shrunk, but also the vertical dimension of doped source/drain regions must be scaled to avoid device punch through and short channel effects. In the past, pn junctions were formed by dopant ion implantation into Si substrate followed by high temperature furnace annealing for dopant activation and implantation damage annihilation.
However, channeling effect and high temperature dopant diffusion limit the formation of shallow junction. This is particularly important for the p+n junction because boron is a light element and diffuses fast in silicon.
In recent years, many advanced junction formation techniques have been studied using low energy ion implantation, low temperature annealing, and rapid thermal annealing process. These new methods are briefly reviewed as follows.
(1) Pre-amorphization of silicon substrate before dopant implantation Pre-amorphization has been widely used to control the channeling
behavior of implanted dopant atoms. After the pre-amorphization of the silicon substrate surface layer, dopant implantation was performed followed by crystal regrowth and annealing process for the junction formation. Many heavy atoms have been used as pre-amorphization species, such as Si [1] and Ge. [2-3] Solid phase epitaxial (SPE) scheme can be used to regrow the crystal from the amorphous layer at a temperature as low as 550 ℃ [4]. The growth rate depends on the element used for pre-amorphization as well as the dopant implanted following the pre-amorphization. A careful annealing process is needed to annihilate the massive defects and dislocation induced by the pre-amorphization.
(2) Elevated source/drain structure
This method is to raise the source/drain regions by depositing a polysilicon (poly-Si) or amorphous silicon (α-Si) film or growing a selective epitaxial Si or SiGe layer. [5-6] Deposition of poly-Si/α-Si film on the source/drain regions needs an additional lithographic step to define the elevated regions, while the selective epitaxial growth of silicon on the source/drain regions does not need such an additional lithographic step.
The elevated source/drain regions made with selective epitaxial growth (SEG) provide a sacrificial layer for silicide formation and an alternative approach for the salicide process. However, the SEG scheme needs a high deposition temperature to obtain good crystallinity in the epitaxial layer.
The fact that high temperature process deteriorates the device performance is the main disadvantage of this method. [7]
(3) Low energy ion implantation [8-10]
This is an extension of the conventional ion implantation technique.
The implantation energy is lower than 1 keV and the implantation dose is typically from 1×1014 to 5×1014 cm-2. The major disadvantage of this method is that no commercial implantation system of such a low energy beam line is available for high throughput mass production with reasonable cost.
(4) ITS/ITM technique
The implant through silicide (ITS) and implant through metal (ITM) processes have been investigated for shallow junction formation. The ITS/ITM process consists of implanting dopants into/through silicide or metal layer and the subsequent thermal annealing to form a silicide-contacted shallow junction [11-14]. The ITS scheme in particular is of much benefit to the formation of shallow junction. This is because metal silicides have a larger nuclear stopping power than silicon for the implanted dopant ions and thus can reduce the channeling effect; in addition, the junction formed by the ITS scheme can be almost free of implant damage, which is mostly confined in the silicide layer. Thus, the post-implant annealing temperature can be lowered while shallow junctions with superb characteristics can be obtained. Moreover, the silicided junction is conformal to the silicide/silicon interface, and thus the possibility of junction penetration by the silicide is reduced.
Boron is used for the extension and source/drain regions of pMOSFETs. Boron offers a high solid solubility, [15-17] which produces
a low resistance, but has a relatively high diffusion coefficient that results in deep junctions. Both the solid solubility and the diffusion coefficient increase with temperature. Therefore, it is difficult to realize a low resistance and shallow junction when using B. For these problems, we employ the ITS scheme which is used for silicide-contacted shallow junction formation.
2.2 Experiment
Samples were fabricated on p-type (100) oriented Si wafers. After a standard RCA clean process. Then, a 400 nm isolation oxide was grown on the wafer by wet oxidation at 1050 for 30 min. The active regions ℃ were defined by the photolithography and etched by BOE (buffered oxide etchant) solution. Next, standard clean was used again to fully remove the contamination. Following, a 200 Å Ni deposited on the wafer in a dc sputtering system with a base pressure of less than 2.5×10-6 torr, using a Ni target in Ar ambient at a pressure of 2×10-3 torr with a deposition rate of about 0.1- 0.2 Å/sec. After the Ni film deposition, the samples were rapid thermal annealed (RTA) at 400 for 30 sec in N℃ 2 ambient to form NiSi. The unreacted Ni film was selectively etched using a solution of H2SO4 : H2O2 = 3 : 1 at 75~85 for 60 sec. The formed NiSi film ℃ thickness was determined by cross-sectional scanning electron microscopy (SEM). Then, the sample of NiSi were implanted with BF2+ / P+ ions at an energy of 20 and 10 k eV to a dose of 1×1013 cm-2. After ion
for 30 / 60 / 90 sec in N2 ambient for the activation dopant, as shown in Fig 2-1. Process recipe is listed in table 2-1.
2.3 References
[1] M. H. Juang and H. C. Cheng, Appl. Phys. Lett. 60, 2092, (1992).
[2] M. C. Ozturk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A.
Rozgonyi, E. Frey, W.-K. Chu, and C. Lee, IEEE Trans. Electron Devices 51, 663, (2004).
[3] K. Suzuki, H. Tashiro, K. Narita, and Y. Kataoka, IEEE Trans.
Electron Devices 35, 659, (1988).
[4] M. Y. Tsai and B. G. Streetman, J. Appl. Phys. 50, 183, (1979).
[5] H. J. Huang, K. M. Chen, T. Y. Huang, T. S. Chao, G. W. Huang, C. H.
Chien, and C. Y. Chang, IEEE Trans. Electron Devices 48, 1627, (2001).
[6] J. J. Sun, J. Y. Tsai, and C. M. Osburn, IEEE Trans. Electron Devices 45, 1946, (1998).
[7] K. Miyano, I. Mizushima, A. Hokazono, K. Ohuchi, Y, Tsunashima, IEDM Tech Digest, p. 433, (2000).
[8] Y. V. Ponomarev, P. A. Stolk, A. C. M. C. Van Brandenburg, C. J. J.
Dachs, M. Kaiser, A. H. Montree, R. Roes, J. Schmitz, and P. H. Woerlee, VLSI Tech. Digest, p. 65, (1999).
[9] D. Kirkwood, A. Murrell, E. Collart, P. Banks, R. Fontaniere, and C.
Maleville, IEEE International Conference on Ion Implantation Technology, p. 633 , (2002).
[10] A. Nishida, E. Murakami, and S. Kimura, IEEE Trans. Electron Devices 45, 701, (1998).
[11] C.-Y. Lu, J. J. Sung, R. Liu, N.-S. Tsai, R. Sing, S. J. Hillenius, and H. C. Kirsch, IEEE Trans. Electron Devices 38, 246, (1991).
[12] Q. Wang, C. M. Osburn, C. A. Canovai, IEEE Trans. Electron Devices 39, 2486, (1992).
[13] R. Angelucci, S. Solmi, A. Armigliato, S. Guerri, M. Merli, A. Poggi, and R. Canteri, J. Appl. Phys. 69, 3962, (1991).
[14] B. S. Chen and M. C. Chen, IEEE Trans. Electron Devices 43, 258, (1996).
[15] F. A. Trumbore, “Solid solubilities of impurity elements in germanium and silicin,”Bell Syst. Tech. J.,vol. 39, pp. 205-233, (1960).
[16] G. L. Vick, and K. M. Whittle, “Solid solubility and diffusion coefficients of boron in silicon,”J. Electrochem. Soc., vol. 116, pp.
1142-1144, (1969).
[17] G. Binning, C. F. Quate and Ch. Gerber, Phys. Rev. Lett., 56, p. 930, (1986).
Chapter 3
Physical Properties and Electrical Characteristics of Boron/Phosphorous Implanted Through Silicide
3.1 Physical Properties boron/ Phosphorous implantation through silicide
3.1.1 Surface morphology by AFM inspection
In 1986, Binning et al. introduced another apparatus for surface characterization in atomic scale, the atomic force microscope (AFM).
Since it can be applied to any types of material and environment, AFM has thus been used widely in surface characterization. Owing to its atomic scale resolution capability, AFM is also powerful equipment for nano-structure fabrication.
We want to inspect the surface morphology of NiSi/ Si interface by AFM.
Because of the roughness between the NiSi/ Si interface related to the junction leakage. We want to know the impact on roughness of temperature.
Fig. 3-1 AFM image shows NiSi/Si interface morphology by 2nd RTP annealing (a) 400 (b) ℃ 500 ℃(c) 600 ℃ (d) 700 for 30 sec. Fig. 3℃ -2
RMS value of the interface roughness versus temperature with / without 2nd RTP annealing. For the 2nd annealing sample, the interface roughness is smoother than the without 2nd annealing sample. Therefore 2nd annealing may improve interface roughness.
3.1.2 SEM cross-sectional view inspection
In order to identify the real thickness of the as-deposited Ni film and the NiSi layer formed, scanning electron microscope (SEM) was used for cross sectional view inspection. Fig. 3-3 shows SEM image of NiSi layer formed by RTP annealing at 400 for 30sec.℃
3.2 Electrical measurements
The electrical properties of the silicide-contacted shallow junction diodes fabricated by the ITS scheme are dependent on a number of factors, including the dopant activation level, implantation damage recovery, silicide/silicon interface roughness, and the distance between the silicide/silicon interface to the junction position. All of these are closely related to the energy and dosage of the dopant ion implantation as well as the dopant activation ability and the drive-in diffusion during the subsequent annealing process; this is especially important for the case of low thermal budget and low energy implantation for the ITS scheme.
3.2.1 I-V measurement
The current transport in metal-semiconductor contacts is mainly due to majority carriers, in contrast to p-n junction, where the minority carriers are responsible. Fig. 3-4 shows four basic transport processes under forward bias.
The four processes are (1) transport of electrons form the semiconductor over the potential barrier into the metal[the dominate process for Schottky diodes with moderately doped semiconductors (e.g., Si with ND ≤ 1017 cm-3) operated at moderate temperatures(e.g., 300 °K)], (2) quantum-mechanical tunneling of electrons through the barrier (important for heavily doped semiconductors and responsible for most ohmic contacts), (3) recombination in the space-charge region [identical to recombination process in a p-n junction] and (4) hole injection from the metal to the semiconductor (equivalent to recombination in the neutral region). [1]
Fig. 3-5 shows the ID-VD characteristic curves of the NiSi/Si junction diode without 2nd RTA by (a) BF2+ implantation and (b) P+ implantation.
It is obvious that the NiSi/Si junction stills to appear the Schottky junction behavior both the BF2+ and P+ implantation. The current transport leads by majority carriers from semiconductor over potential barrier into the metal.
Fig. 3-6 shows the forward ID-VD characteristic curves of the NiSi/Si junction diode with 2nd RTA 30 sec by (a) BF2+ implantation and (b) P+ implantation. We after discovered the curve presents the ohmic contact the linear curve to pass through 2nd RTA 30 sec. The forward currents rise
along with the annealing temperature. After 550 ℃ maximize starts to reduce along with the temperature rise. According to the extrapolation:
NiSi/Si interface damage is recovered and roughness repaired at 550
℃~650 ℃. Fig. 3-7 shows ID-VD characteristic curves of the NiSi/Si junction diode with 2nd RTA 30 sec by (a) BF2+ implantation and (b) P+ implantation. The ID-VD characteristic curves approximate linear. We knew schottky contact turns ohmic contact after the annealing process.
Fig. 3-8 Forward bias current density versus annealing temperature for the NiSi/Si junction diodes fabricated with (a) BF2+ and (b) P+ implantation at various annealing time. Forward bias current density drops along with the time and the temperature rise. High temperature and long time RTA process may promote interface state. Cause the tunneling current is reduction. [2-3]
3.2.2 Reverse leakage current density
Fig. 3-9 shows the reverse bias current density (JR) versus annealing temperature for the NiSi / Si junction diodes with an area of 0.000625 cm2 (250 × 250 µm) measured at a reverse bias of －5 V. The reverse bias current density (JR) is determined by directly dividing the measured current by the diode’s area. Roughness of the silicide/Si interface in a shallow junction may lead to the formation of localized Schottky contacts or the agglomeration-induced local silicide spiking, resulting in the increase of reverse bias current. After annealing at temperature above 600
℃ 60 sec and above 500 ℃ 90 sec, the increased activation level, damage recovery level, and interface doping concentration should all have should all have contributed to better junction characteristics. [4]
3.2.3 C-V measurement and doping profile extraction
The capacitance-voltage (C-V) technique relies on the fact that the width of a reverse-biased space-charge region (scr) of a semiconductor junction device depends on applied voltage. This scr width dependence on voltage lies at the heart of the C-V technique. The C-V profiling method has been used with Schottky barrier diodes, p-n junction, MOS capacitance, and MOSFETs.
We consider the Schottky barrier diode. The semiconductor is p-type with doping density ND . A dc bias V is applied to the metal contact. The reverse bias produces a space-charge region of width W. The differential or small signal capacitance is defined by
dQS
C= − dV (3-1)
Where QS is the semiconductor charge. The negative sign accounts for more negative charge in the semiconductor scr (negatively charged ionized acceptors) for higher positive voltage on the metal. The capacitance is determined by superimposing a small-amplitude ac voltage
v on the dc voltage V. The ac voltage typically varies at frequencies of
10 kHz to 1MHz with amplitude of 10 to 20 mV, but other frequencies and other voltages can be used.
Let us consider the diode to be biased to dc voltage V plus a sinusoidal ac voltage v. Imagine the ac voltage increase from zero to a small positive voltage adding a charge increasing dQm to the metal contact.
The charge increment dQm must be balance by an equal semiconductor charge increment dQS for overall charge neutrality, where dQS is given by
( ) dQ qAN W dW
S = − A (3-2)
The depletion approximation is employed in Eq. (3-2), i.e., the mobile carrier densities p and n are assumed to be zero in the depleted space-charges region. Furthermore, we assume N = 0D for this p-type substrate and we also assumed that all acceptors are fully ionized at measurement temperature. When that is not the case, as for acceptors and donors with energy levels deep within the band gap, true dopant density profile may not be measured.
The charge increment dQS, comes about through a slight increase in the scr width. From Eqs. (3-1) and (3-2) we find
dQS ( )dW
C qAN W
dV A dV
= − = (3-3)
In going from Eq. (3-2) to (3-3), we have neglected the term dN ( )W dV
A .
The assumes that N
A dose not vary over the distance dW , or variation of N
A over a distance dW cannot be obtained with the C V−
technique. The capacitance of in these equation is given in units of Fnot / 2
F cm .
The capacitance of a reverse-biased junction, when considered as a parallel plate capacitor, is
0
KS A
C W
= ε (3-4)
Differentiating Eq. (3-4) with respect to voltage and substituting dW dV
into Eq. (3-3) gives
which can also be written as
2 2 dependence in these expressions.
Since the area appears as A2, it is very important that the device area be width dependence on capacitance as
0
KS A
W C
= ε (3-6)
Equations (3-5) and (3-6) are the key equations for doping profiling. The doping density is obtained from a C V− curve by taking the slope
/
dC dVor from a 1/ C2−V curve by taking the slope d(1/C2) /dV . The depth at which the doping density is evaluated is obtained from Eq. (3-6).
For a Schottky barrier diode there is no ambiguity in the scr width since it can only spread into the substrate. Space-charge region spreading into the metal is totaling negligible. The doping profile equations are equally well applicable for asymmetrical pn junctions with one side of the heavily doped side is 100 or more times higher than that of the lowly doped side, then the scr spreading into the heavily doped region can be neglected, and Eqs. (3-5) and (3-6) hold. If that condition is not met, the equation must be modified or both doping density and depth will be in error. The correction, however, is fraught with difficulty. It has been proposed that no unique doping profile can be derived from C V− measurements under those conditions. If the doping profile of one side of the junction is known, then the profile on the other side can be derived from the measurements. Fortunately, most pn junctions used for doping density profiling, are of the p n+ and n p+ type, and corrections due to doping asymmetries are not necessary.
Fig. 3-10 shows the capacitance-voltage characteristics of Schottky junction diodes implanted (a) BF2+ and (b) P+ without 2nd RTA. We
is shown in Fig. 3-11. We may observe the dopant to be able to approach NiSi/Si interface to pile up along with annealing temperature. That is called dopant segregation (DS). [5-6] Boron concentration near the NiSi/Si interface was about 1020 cm-3 after 550 ℃ annealing; it decreased slightly after 650 ℃. A low temperature annealing was able to accumulate the boron concentration near the NiSi/Si interface up to a very high value. At the 650 ℃ annealing, the boron concentration at NiSi/Si interface decreased to about 1018 cm-3 and significant boron diffusion was observed. Phosphorous concentration was about 1020 cm-3 near the NiSi/Si interface. After 650 annealing; it has not degradation ℃ phenomenon. Because of the implanted boron sample to occur transient enhanced diffusion in the early stage of the subsequent annealing process.
[7-9] The Active charge versus annealing temperature for (a) Boron and (b) Phosphorous implant is shown Fig. 3-12.Obviously the active amount of boron is more than phosphorous about two times.
[7-9] The Active charge versus annealing temperature for (a) Boron and (b) Phosphorous implant is shown Fig. 3-12.Obviously the active amount of boron is more than phosphorous about two times.