1.2 Motivation
With the improvement of the process technology, when the devices scale down, how to suppress the leakage current effectively is our target. The shrinkage of channel length is the most effective way to promote the driving current of a transistor. Another way to improve the Ids is increasing the Cox (eq-1) by scaling down oxide thickness (eq-2), therefore finding High-k materials, and making them have thicker true thickness but have thinner EOT (Equivalent Oxide Thickness), is one of our researching direction.
Ids = 1/2Coxµn(W/L)(VGS－－－－Vt)(VDS) [eq-1-1]
Where µn is the effective mobility, Cox is the gate capacitance, W is the channel width, L is channel length. Obviously, drive current is inversely proportional to the channel length L. Therefore, the shrinkage of channel length is the most effective way
to promote the driving current of a transistor.
[eq-1-2]
Generally there are several point we should care about high-k materials (1) low
leakage current. (2) low interface trap density. (3) low bulk trap. (4) good thermal stability. (5) good reliability. But now the subject matter of high-k materials is the high interface trap density lead to high leakage current and not available to work on devices. Therefore, this thesis is researching different surface treatment after depositing high-k materials to lower interface trap and abate Fermi level pinning effect. We expect that it is useful to increase high-k materials feasibility and will replace SiO2 in the future.
1.3 The Choice of High-K Materials
There are many factors we should think about when we choose high-k materials.
First, the most of high-k materials don’t have wide enough bandgap, therefore it is easy for both electron and hole through the dielectric, and lead to large leakage current. The bandgap of high-k materials are present in Fig1-1.
Second, materials with slightly high-k value than thermal oxide don’t have low leakage enough to conform to our criteria, and large k value materials have poor thermal stability generally, and will suffer from larger fringing field and degrade short channel characteristics [5], the fringing effect will make extra field lines terminate in the S/D region and share the charge controllability with the gate. This will lower the potential in the channel for electron, and influence the gate control ability. Third, most of high-k would react with the Si, there are two possible reaction, one is [eq1], after the high temperature process, the metal in high-k materials would separate out, and the oxygen would react with the Si to form an interfacial layer between silicon subtract and high-k.
MOx + Si i i i →→→→ M + SiO M + SiO M + SiO M + SiO2 2 2 2 [eq1-3]
The other is the high-k materials react with Si to form silicide [eq4], the formation of the silicide would provide the transport path to carrier, and induce large leakage current.
MOx + Si i i i →→→→ MSi MSi MSi MSiyyyy + SiO+ SiO+ SiO+ SiO2 2 2 2 [eq1-4]
The interfacial layers would lower dielectric constant, therefore the dimension size will hard to scale down.
Fourth, the interface quality and morphology between high-k and Si substrate should be considered. The quality would affect the carrier mobility in the channel, and make mobility degradation, lower the device performance. Another aspect, the film morphology is also important, during the all process, the device has to go through many high temperature thermal treatment, including annealing, dopant activation annealing, the thermal budget will affect the film morphology, high temperature process would make high-k dielectric change phase, from the amorphous phase to the polycrystalline phase, lead to large grain boundaries which supply leakage path and induce large leakage current.
Considering all of above, we should choose the appropriate high-k material with more advantage and less drawback to device. Among High-k materials, HfO2 can be used due to its relatively high dielectric constant(~25), its relatively high free energy of reaction with Si, and its relatively high band gap(5.68ev), the properties comparison of SiO2 and HfO2 is showed in table 1-1. If we add Al during deposition process to form HfAlO can increase crystallization temperature, and the concentration of Al is higher, the crystallization temperature is higher too . If the crystallization
temperature is low, grain boundaries in crystallized gate dielectric can be the fast paths for oxygen or dopants diffusion into gate dielectric and even into FET channel region in silicon substrate causing uncontrolled interfacial layer growth at the high-K/Si interface, threshold voltage instability and defect generation. Adding Al during deposition process can also prevent the formation of Hf silicide between dielectric and Si substrate.
Therefore, HfAlO can have better thermal stability than HfO2, but HfAlO also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation.
1.4 Fermi Level Pinning
There is a problem when we use high-k dielectric, the phenomenon is called Fermi level pinning (FLP) and it will make the effective work function of gate materials be controlled difficultly. It means that Φm,eff differs from Φm,vac, therefore the flatband voltage is almost independent upon metal gates, FLP is a consequence of interfacial reaction or interfacial charge exchange between gate electrode and gate dielectric, the reasons of Fermi-level pinning is intrinsic charge exchange.
The MIGS (metal induced gap states) and VIGS (virtue gap states) theory are used to explain the intrinsic charge exchange, The origin of the VIGS is from the dangling bonds of uncoordinated surface atoms. These dangling bonds produce surface states which continuously disperse in the energy gap of dielectrics. The surface states are confined at the surface to exponentially decay into vacuum and into solid . MIGS assumes that the exponentially decaying bulk states are the main component of the
surface states of the dielectric and that the states of the metal in contact with the dielectric couple to its surface states exchanging in order to maintain local charge neutrality. Free electrons in the metal penetrate into the dielectric at the interface and cause the interface charges. The amount of transferred charges is dependent upon the charge neutrality level (ECNL) and metal Fermi level (EFm). ECNL is a branch point of surface energy level, which is usually near the mid-gap of dielectric energy band. No charge will be transferred across the interface when the EFm is coincided with ECNL. With the surface level above or below ECNL, the net charge of the surface is negative and positive on the dielectric side, respectively. In the case where EFm is above ECNL, the dipole layer created at the interface will be negative on the dielectric side. This dipoles will tend to drive the EFm close to ECNL, and hence the effective work function (Φm,eff) will differ from the work function in vacuum (Φm,vac). The effective work function takes account the effects of interfacial dipoles and is determined by density of states N, the surface states penetration depth δ, and the permittivity of the dielectric. (eq 1-5). And it also can be estimated from the empirical (eq 1-6)
whereε∞ [6] is the electronic component of the dielectric constant.
Figure 1-2 shows two critical conditions, Fermi Level Free S=1, and Fermi Level Fixed S=0. A high-k dielectric will lower the slope parameter S and highly pin the Em,eff in the ECNL since the electronic component of the dielectric constant is high.
This indicates that high-k materials will suffer from serious Fermi-level pinning effect, and induce effective work function close to ΦCNL. To obtain suitable effective work function, metal gates on high-k materials for pMOSFETs (nMOSFETs) should have higher (lower) work function to compensate the effects of Fermi-level pinning. Another theory is that Fermi level pinning in high work function materials is governed by the O vacancy generation and subsequent formation of interface dipole near gate electrodes due to the electron transfer, and it in low work function is governed by O interstitial formation, therefore the work function pinning free region appears due the difference in the mechanism of Fermi level pinning of high and low work function materials. And the type of metal silicide is also affect the pinning position, n-like metal silicides are usually located between the pinning position of n+ and p+ poly-Si gate, and those of p-like metal silicides are located near the pinning position of p+-poly-Si gates , the pinning position is shown in Figure1-3
1.5 Organization of This Thesis
.In this thesis have four chapters in this dissertation. In chapter 1 , we make an introduction to describe the background of the Semiconductor technology and
discuss the possible issues that we may meet during the dimensions scaling down. In addition , we would talk about the hopeful solutions to overcome the physical limits.
The possible solution is the alternative high dielectric constant materials. They would replace the traditional SiO2material in the gate materials.In chapter 2 , we will introduce the properties of the high dielectric constant material hafnium oxide ( HfAlO ), and describe the experimental procedures, electrical measurements, material analysis. In chapter 3 , we will investigate the electrical properties of HfAlO thin film including two surface treatment UV ozone treatment and N2Otreatment.
before HfAlO deposition and two interface treatment UV ozone treatment and NH3 treatment accompany with RTA treatment after HfAlO deposition We will discuss the experimental results.At the end of this thesis, conclusions are given in chapter 4.
Fig 1-1 The bandgap of high-k materials 1.6
3.3
Physical parameters
SiO2 HfO2
Dielectric constant
3.9 21-25
High-k/Si barrier
height 3.1-3.5 1.5
Energy band gap
9 6
Breakdown
field(MV/cm) 10-15 3-6.7
Structure Type
Amorphous Polycrystal (400~900℃) Interface state
density, Dit(cm-2ev-1) <1010
8X1010 J(A/cm2) at 1V for
EOT=1nm >1 <1X10-4
Contact stability
with Si(kcal/mol) Stable 47.6
Table 1-1 properties comparison of SiO2 and HfO2
Figure 1-2 The critical Fermi level of metal gate on dielectric. the effective work function of metal on dielectric is the same as in vacuum while the interface is perfect. The work function is fixed to the dielectric-charge-neutral level while the
interface-state density is high. the interface states are caused by both intrinsic states (MIGS, ViGS) and extrinsic states (defect levels).
Fig 1-3 Schematic illustration of the Fermi level pinning observed in poly-Si and n-like, p-like MSix gates
Chapter 2
Experimental Procedures and measurements
2-1 Properties of Hafnium Aluminum Oxide
HfAlO film was deposited by electron-beam evaporation method. The background pressure of the main chamber was 10−6–10−7 Pa, and the substrate temperature was kept at 300 °C. High purity sintered HfO2 and Al2O3 pellets were coevaporated at the rate of 0.2–0.5 Å/ s, We use Hafnium aluminum oxide (HfAlO) to replace Hafnium oxide (HfO2), because of the some poor characteristics of HfO2.[7]When the HfO2 is thin, it exhibit poor thermal stability and tend to crystallize at low temperature of 400-500℃, this will cause significant increases in leakage current, therefore it can increase crystallization temperature by the incorporation of Al2O3 forming the HfAlO alloy [8]-[12].. The comparison of leakage current in different annealing temperature of this two materials is showed in Fig 2-1. we can observed the leakage current of HfO2 at higher temperature is larger than HfAlO at same RTA temperature.
2-2 Experiment Process of PMOSFET with Treatment Before HfAlO Deposition
MOS transistors was fabricated on 4-inch p-type Si with ( 1 0 0 ) orientation.
After removing the native oxide, RCA clean was performed with HF-dip last, followed by UV ozone and N2O treatment. After surface treatments sample with a high temperature 900oC 60 seconds was used for density interface oxide. After
surface treatment HfAlO was deposited at room temperature and 7.6E-3 torr by ion sputter system. Followed by a high temperature 900oC post deposition annealing (PDA) in the nitrogen ambient for 30 seconds in order to improve the film quality. A 200nm undoped polycrystalline silicon (poly-Si) layer was directly deposited by low pressure chemical vapor deposition (LPCVD) on top of HfAlO films After the gate electrode was patterned by lithography and etching processing. Then implant As 20 KeV dose 5E15 #/cm2 after that activation was done at 950 oC by rapid thermal annealing (RTA) for 30seconds in the nitrogen ambient. After a 500nm SiO2 passivation was done by PECVD. Define the contact hole by the lithography and etching passivation SiO2 and high k layer in order to silicon contact whit metal. Al was deposited by thermal evaporation system. Metal pad is defined by lithography and etching. Backside contact was formed by thermal evaporation. Fig 2-2 , Fig2-3 show the cross section and the process flow of pMOS transistor.
2-3 Experiment Process of Capacitance with Treatment Before and
After HfAlO Deposition
Wafers were cleaned by standard RCA processes with HF-last for the removal of the particles and native oxides. and UV ozone was used to grow an ultra-thin ozone oxide about 9~11Å, after UV ozone surface treatments, a high temperature 900oC 60 seconds was used for densify ozone oxide. HfAlO was then deposited at room temperature and 7.6E-3 torr by ion sputter system, followed by UV-ozone or plasma NH3 treatment and then a different high temperature (as deposition, 800oC, 900oC,1000oC) post deposition annealing (PDA) in the nitrogen ambient for 60 seconds were investigated, before Aluminum metal gate deposition which was created by a thermal evaporation system. After gate electrodes patterned and
backside contact was formed by thermal evaporation. The process flow and structure are shown in Fig 2-3, the area of capacitors is 4.5216×10-4 cm2
2-4 Interface Treatments Before HfAlO Deposition
The control of SiO2-like interface between high-κ dielectrics and silicon substrate pays more and more important, since the device performances and reliability characteristics are strongly affected by the interface quality. Nitridation of the Si surface using N2O prior to the deposition of high-κ gate dielectrics has been shown to be effective in achieving the low EOT (equivalent oxide thickness) and preventing boron penetration [13], [14]. However this technique results in higher interface charges [15], which leads to higher hysteresis and reduced channel mobility.
Ozone-formed oxide (ozone oxide) has superior characteristics. Even when the formation temperature is less then 400°C, ozone oxide has a high film density comparable to that of the device-grade oxide film formed at higher temperature, a low interface trap density, and a much thinner structural transition layer near the SiO2/Si interface [16]. The ozone surface treatment was employed to improve the interface quality between HfAlO and silicon substrate.
2-5 Interface Treatments After HfAlO Deposition
The interface treatment can be performed with the surface treatment before metal deposition and it can be plasma treatment or reactive gas annealing. The interface treatment can change the texture bonding, and reduce defects such as dangling bonds at the interface between metal gate and dielectric as well as incorporation of extra impurities. The changes of interface and incorporation will upset a balance within the primary interface. According the past research the direct contact of high-k materials
and Si-substrate will have many issues. We need high quality interface of dielectric/Si or metal/dielectric with low density of interface states (Dit~2x1010 states/cm2) arising from unsaturated surface bonds and other electrically active imperfections. Interface states will lead to low on-current because of carrier mobility is limited by scattering at the interface with the vertical electric fields present in the channel. Therefore in this thesis we try two surface treatment including ozone plasma and NH3 plasma after HfAlO deposition to make the higher quality interface between metal gate and high-k dielectric, or change the texture bonding of HfAlO.
2-6 Electrical Measurement
The Capacitance-Voltage (C-V) and Current-Voltage (I-V) characteristics were measured by Hp-4284 and Hp-4156. The dielectric constant (k-value) is then calculated from the measured capacitance at accumulation mode. The equivalent oxide thickness (EOT) was extracted by fitting the measured high-frequency (100 kHz) capacitance-voltage (C-V) data under accumulation condition. UCLA CVC simulation program was utilized to obtain the accurate flat band voltage (VFB). The C-V hysteresis phenomenon was measured by sweeping the gate voltage from accumulation to inversion then back. The tunneling leakage current density-electric field (J-E) and the reliability characteristics of MOS capacitors were measured by semiconductor parameter analyzer HP 4156C.
2-7 Reliability Measurement
We observe the reliability from stress-induced leakage current (SILC),, measurements. SILC were measured at room temperature, gate bias=--4 for RTA after
surface treatment and -3V for RTA before surface treatment, the J-E curves were measured at 10 sec 20sec 50sec 100sec 200sec 1000sec respectively during stress.
Fig 2-1 The leakage current of ALD 30nm of HfO2 and HfAlO after rapid thermal annealing of 800000℃℃℃℃ and 950000℃℃℃ ℃
Gate voltage
-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
Gate current (A/cm2 )
10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1
PDA 800 for HfAlO PDA 950 for HfAlO PDA 800 for HfO2 PDA 950 for HfO2
Define Active region
RCA Clean with HF-last
Surface Treatment
High_k Deposition
Post Deposition Annealing
Poly Gate Deposition
Define Gate & Patterning
Ion implant
Define by Lithography and pattered
One is Ozone surface treatment and the other is N2O treatment.
RTA 800oC 60seconds was used.
A 200nm poly silicon was deposited by LPCVD.
Define by Lithography and pattered
Implant As 20KeV dose:5e15#/cm2
Activation RTA 950oC 30seconds was used and
S/D was formed.
Fig 2-2 The diagram of process flow of pMOS transistor
Define Contact hole
& Patterning
Aluminum Deposition
Define by Lithography then etching passivation oxide and high_k.
Define metal and etching meatal
500nm aluminum was deposited by thermal evaporation system.
Backside contact
Define by Lithography and pattered
500nm aluminum was deposited by thermal evaporation system.
Figure 2-3 The cross section of pMOS transistor.
Al Pad
Al Backside Contact Si Substructure
FOX FOX
Surface treatment High k Gate dielectric
S D
Poly Gate Passivation Oxide
Surface treatment by UV-ozone or NH3
Fig 2-4 The diagram and structure of process flow of capacitance Si-Substract
Chapter 3
Result and Discussion
3-1
The Electrical Characteristics of Surface Treatment Before HfAlO Deposition
Nitridation of the Si surface using N2O prior to the deposition of high-κ gate dielectrics has been shown to be effective in achieving the low EOT and preventing boron penetration [17], [18]. However this technique results in higher interface charges [19], which leads to higher hysteresis and reduced channel mobility. So we use UV ozone to oxidation, ozone and atomic oxygen, produced by exposure of atmospheric oxygen to ultraviolet radiation, Figure 3-1 showed the schematic diagram of UV ozone system. The ozone generator (AnserosPAP-2000) decomposed the oxygen molecular to generate ozone gas by high electrical field. The ozone gas was mixed with UV lamp in chamber. By changing the oxygen flow and ozone generation power, the ozone concentration in the chamber could be adjusted.
Ozone-formed oxide (ozone oxide) has superior characteristics. Even when the formation temperature is less then 400°C, ozone oxide has a high film density comparable to that of the device-grade oxide film formed at higher temperature [20], a low interface trap density [21], and a much thinner structural transition layer near the SiO2/Si interface [22]. The ozone surface treatment was employed to improve the interface quality between HfAlO and silicon substrate. Figure 3-2 shows the drain
current (Id) versus the drain voltage (Vd) characteristic for UV ozone surface treatment and N2O surface treatment. The drain current is larger for the UV ozone surface treatment. Fig 3-3 shows the transconductance characteristics, we observe that transconductance peak value of UV ozone treatment is higher than samples with N2O rsurface treatment. Figure 3-4 and Figure 3-5 shows the drain current (Id ) versus the gate voltage (Vg) of pMOSFETs with and UV ozone treatment and N2O treatment. We can see that the substhreshold swing (S.S.) of UV-ozone treatment is 75.26 mV/decade which is better than the 91.2mV/decade of N2O treatment.
In this section, we also research the relationship between charge pumping and mobility through devices in different surface treatment. Unlike SiO2 films, high-k films are more susceptible to charge trapping. Charge trapping is arguable one of the most important issue in CMOS devices with high-k gate dielectrics, because of the large amount of bulk traps present in the high k films [23]-[26]., and they may cause mobility degradation [27]-[30] and Vth instability [31]-[40], it used to use charge pumping to measure interface state density in MOSFET devices by utilizing the exclusion of gate leakage to calculate interface state density in high-k dielectric. We consider an p-channel device of gate length L and width W Evaluate mobility by
In this section, we also research the relationship between charge pumping and mobility through devices in different surface treatment. Unlike SiO2 films, high-k films are more susceptible to charge trapping. Charge trapping is arguable one of the most important issue in CMOS devices with high-k gate dielectrics, because of the large amount of bulk traps present in the high k films [23]-[26]., and they may cause mobility degradation [27]-[30] and Vth instability [31]-[40], it used to use charge pumping to measure interface state density in MOSFET devices by utilizing the exclusion of gate leakage to calculate interface state density in high-k dielectric. We consider an p-channel device of gate length L and width W Evaluate mobility by