Chapter 1 Introduction 1
1.4 Motivation
In recent years, the demands of cost down in production lines and products are
becoming most important for device production. The selection of materials and design
of device structure are two of the key points to reduce cost. Therefore, we want to
demonstrate a potential resistive random access memory (RRAM) with cheap
materials and simple fabrication process which can integrates with the well
developing process in semiconductor industry nowadays. Moreover, we expect the
RRAM can apply to organic electronic products and even manifest the flexible
property.
In this work, we demonstrate an inorganic RRAM with low cost materials and
simple MIM structure of Ag/SiO2/p+-Si. Furthermore, we improve the endurance of
device by post-annealing treatment on SiO2 thin film. The performance and
mechanisms of devices are also investigated. Later, we fabricate organic RRAM with
bi-layer and tri-layer structure, respectively and both devices exhibit high ON/OFF
current ratio. Moreover, we observe the endurance improvement by substituting the
metal electrode for the tri-layer structure.
15
Chapter 2. Inorganic RRAM Using Sputtered SiO
2films
In this chapter, we focus on the research on Ag/SiO2/p+-Si structure with
different post-annealing SiO2 conditions. We observe that the device with RTA 800oC
exhibits the best performance of a memory device. Furthermore, we observe a
transition of mechanism for the high conductance states which are different from the
filamentary mechanism dominated RRAM with MIM structure.
2.1. Fabrication of the RRAM with Ag/SiO
2/p
+-Si Structure
The metal-insulator-metal (MIM) device structure of the inorganic RRAM in this
study is shown in Fig. 2.1. First, p+-type silicon substrate is cleaned according to a
standard RCA clean process. Then, silicon dioxide (SiO2) is deposited onto cleaned
p+-type silicon substrate at 5x10-3 torr using sputter at room temperature. The
sputtering power is at 100W, and the thickness is fixed at 100nm. After deposition,
two samples are treated as post-annealing using rapid thermal annealing (RTA) with
600oC and 800oC, respectively. Finally, an Ag electrode, 100nm thick is evaporated
through metal mask with 2mm x 2mm square pattern onto as-deposited, 600oC and
800oC RTA treated samples. The parameters of fabrication process are shown in Table
2.1.
Fig. 2.1: Schematic diagram of
on SiO2 thin film: (a) as-deposited, (b) RTA
Table 2.1: The parameters of fabrication process of Device
SiO2 thin film
RTA temp.
Electrode (Ag)
2.2. Electrical Characteristics
In our experiment, the
Hewlett Packard 4156A (HP 4156A) semiconductor
The p+-silicon substrate is
electrode. In addition, the scanning interval of voltage
sweeping mode. Fig. 2.2
and 800oC RTA treated samples, respectively
: Schematic diagram of Al/SiO2/p+-Si structure with different RTA conditions
deposited, (b) RTA 600oC, (c) RTA 800oC.
The parameters of fabrication process of Al/SiO2/p+-Si
Sample A Sample B Sample C
100nm
as deposited 600oC 800o
100nm
Characteristics of Ag/SiO
2/p
+-Si RRAM Devices
n our experiment, the electrical characteristics of devices are measured using
Hewlett Packard 4156A (HP 4156A) semiconductor analyzer in ambient environment.
is grounded, and all bias conditions are applied on the
In addition, the scanning interval of voltage is set to 100mV per step in
Fig. 2.2 shows the electrical characteristics of as-deposited, 600
RTA treated samples, respectively. Initially, this device ke
with different RTA conditions
, and all bias conditions are applied on the silver
set to 100mV per step in
deposited, 600oC
. Initially, this device keeps at low
17
conductance state with low current level. However, when sweeping voltage exceed to
threshold voltage, 4V, 4V and 4.5V, which are individually corresponding to
as-deposited, RTA 600oC and 800oC treated samples, an abruptly increase of current is
observed. Then, devices keep at high conductance state with a high current level. The
sweeping process switches the device form low conductance state (OFF state) to high
conductance state (ON state), which is called writing process (green squares line).
When the sweeping voltage from 0V to 5V is applied again, these devices still hold at
high conductance state with high current level, which is called reading process
(magenta circles line). At third sweeping process, the reverse voltage from 0V to -4V
is applied. A noticeable drop of current from high conductance state to low
conductance state is observed. After the reducing of current, all devices are turn back
and kept at low conductance state with a low current level, which is called erasing
process. The parameters of performance of as-deposited, RTA 600oC and 800oC
treated samples are listed in Table 2.2. The Vt, Vth, and ON/OFF current ratio increase
with increasing RTA temperature.
-4 -3 -2 -1 0 1 2 3 4 5
19
Table 2.2: The parameters of electrical measurements of Al/SiO2/p+-Si devices Condition ON/OFF ratio Transition Voltage Threshold Voltage
as-deposited 105 ~2.5V 4V
600oC RTA 105 ~3V 4V
800oC RTA 106 ~4V 4.5V
Fig. 2.3 shows the long retention time over 5000 seconds of samples with
different RTA conditions, and exhibited quite stable ON/OFF current ratio without
any degradation during the retention time measurement. The current level of ON and
RTA 800
oC
(c)
OFF states for samples with different RTA conditions in retention time measurement
are shown in Table 2.3.
0 1000 2000 3000 4000 5000 10
-130 1000 2000 3000 4000 5000
10
-1321
0 1000 2000 3000 4000 5000 10
-1310
-1010
-710
-410
-1High conductance state Low conductance state
Current (A)
Time (sec.)
Fig 2.3: The retention times of Al/SiO2/p+-Si structure with different RTA conditions
on SiO2 thin film: (a) as-deposited, (b) RTA 600oC, (c) RTA 800oC.
Table 2.3: The measurements of retention time of Al/SiO2/p+-Si structure with different RTA conditions
Condition ON current OFF Current Retention time
as-deposited 10-4 10-9 over 5000s
600oC RTA 10-3 10-9 over 5000s
800oC RTA 10-3~10-4 10-10~10-13 over 5000s
The cycle times of (operation), also called endurance test, is one of the most
important properties about the performance of a memory device. For investigation,
RTA 800
oC
(c)
the writing, reading, erasing and reading processes are executed in sequence by 5V,
1V, -4V, and 1V AC pulse for devices with different RTA conditions. To ensure the
consistence of measurement, here we apply the same writing, erasing, and reading
voltages on all devices. As shown in Fig. 2.4, the cycles of as-deposited, RTA 600oC
and 800oC treated samples are 80, 90, and 280 times, respectively. We observe that the
cycles increase with increasing RTA temperature, and the high and low conductance
currents are becoming more stable with increasing RTA temperature, especially at
800oC. Obviously, the as-deposited device shows a large perturbation between the
high and low conductance current, and device with RTA 800oC treatment shows the
most cycle times and best performance. In short, the endurance of Ag/SiO2/p+-Si
structure is improved by increasing RTA temperature on SiO2 thin film. The current
levels of ON and OFF states with different RTA conditions in endurance
measurement are shown in Table 2.4.
23
0 100 200 300 400 500 10
-1310
-1010
-710
-410
-1Current (A)
Cycles
High conductance state Low conductance state
Fig 2.4: The write-read-erase-read cycles of Al/SiO2/p+-Si structure with different
RTA conditions on SiO2 thin films: (a) as-deposited, (b) RTA 600oC, (c) RTA 800oC.
Table 2.4: The measurements of endurance of Al/SiO2/p+-Si structure with different RTA conditions
Condition ON current OFF Current Cycles
as-deposited 10-4 10-6~10-9 80
600oC RTA 10-3~10-5 10-7~10-9 90
800oC RTA 10-3~10-4 10-7~10-10 280
RTA 800
oC
(c)
25
2.3. Mechanism and Discussion 2.3.1. Mechanism
At first, we investigate the optical properties of SiO2 thin film using Raman
scattering measurements. As shown in Fig. 2.5, the intensity of the peak at 610nm
increases with increasing RTA temperature, and it indicates the 3-fold ring defects are
produced by thermal compressive stress [29]. Therefore, we know that the properties
of SiO2 thin films are varied after RTA treatment, and this result may affect the carrier
transportation and mechanism of resistive switching in the SiO2 thin films.
400 450 500 550 600 650 700 0.5
Fig. 2.5: Raman spectrum of SiO2/p+-Si structure with as-deposited, RTA 600oC, and
RTA 800oC treatments on SiO2 thin films.
The formation of conductive filamentary paths in oxide films dominates the
resistive switching has been widely discussed and proposed. To verify the mechanism as-deposited RTA 600oC RTA 800oC
of resistive switching of the as
force microscope (c-AFM) to scan the SiO
2.6 shows the c-AFM image of the as
channels are observed. This result indicate
similar conductive filamentary property in the high conductance state. However, such
few conductive channels are probably not the only source
resistive switching.
resistive switching of the as-deposited SiO2 thin film, we use the conductive atomic
AFM) to scan the SiO2 thin film, which keeps at ON state
AFM image of the as-deposited SiO2 thin film, a few conductive
his result indicates the as-deposited SiO2 thin film m
similar conductive filamentary property in the high conductance state. However, such
few conductive channels are probably not the only source, which is
conductive atomic
keeps at ON state. Fig.
thin film, a few conductive
thin film may have
similar conductive filamentary property in the high conductance state. However, such
dominating the
27
Fig. 2.6: The c-AFM images of SiO2/p+-Si structure: (a) 2-D, and (b) 3-D.
If the conductive filamentary property originates from silver cations, we can
expect the current in high conductance state will decrease with increasing temperature
due to the metallic property. To verify the point above mentioned, the current-voltage
measurements of as-deposited, RTA 600oC, and 800oC treated samples under different
temperature are investigated. As shown in Fig. 2.7, the current-voltage relation versus
temperature shows a clear independence, it suggests the carrier transport in high
conductance state isn’t dominated by metallic filamentary path. In addition, the
temperature-independent property also implies the high conductance current, in the
as-deposited sample, isn’t dominated by Poole-Frenkel emission.
300 320 340 360 380 400 10
-710
-610
-510
-410
-310
-2ON-state Current (A)
Temperature (K) as-deposited
RTA600oC RTA800oC
Fig. 2.7: The current-voltage measurements of as-deposited, RTA 600oC, RTA 800oC
treated samples under various temperatures from 298K to 398K.
2.3.2. Curve Fitting of I-V Currents
Mechanism of filamentary path formation and rupture has been proposed to
explain the resistive switching. According to the filamentary model, the high
conductance current exhibits an ohmic conduction property, it also means that current
(I) will proportion to biased voltage (V1). Therefore, we investigate the transport
characteristics by analyzing the I-V relationship. Fig. 2.8 illustrates the I-V
relationship of the high conductance state in a log-log scale for the various treated
samples. As can be seen, all of the curves are well fitted with the linear form, meaning
that, space charge limited current (SCLC) in the presence of traps is responsible for
29
carrier transport at the high conductance state. However, the slopes of the fitting curve
are about 1.6 and 1.8 for as-deposited, and RTA 600oC treated samples, respectively,
suggesting not only SCLC properties but also resistive properties in both samples. In
addition, the slope of the fitting curve for RTA 800oC treated sample is close to 2. Due
to the results of the curve fitting about the high conductance state, we observe a
transition of carrier transport mechanism from SCLC combined with resistive
property to pure SCLC property with different RTA conditions. The results of curving
fitting are sorted out and displayed in Table 2.5.
-0.8 -0.4 0.0 0.4 -5.5
-5.0 -4.5 -4.0 -3.5 -3.0
log(I)
log(V) Original Data Linear Fit
as-deposited
(a)
-0.8 -0.6 -0.4 -0.2 0.0
Fig. 2.8: Curve fitting of the I-V curves of the high conductance state of Al/SiO2/p+-Si
structure in a log-log plot: (a) as-deposited, (b) RTA 600oC, (c) RTA 800oC.
RTA 800
oC
(b)
(c)
RTA 600
oC
31
Table 2.5: Fitting results of the high conductance states of Al/SiO2/p+-Si structure with different RTA conditions
Condition Slope (S) Indicated Mechanism
as deposited 1<S<2 SCLC and ohmic property
600oC RTA 1<S<2 SCLC and ohmic property
800oC RTA S~2 SCLC
In order to confirm the probable mechanism for carrier transport in the high
conductance state, the device with RTA at 800oC is compared with the as-deposited
and RTA at 600oC ones. Since a large amount of defects exist in SiO2 thin films, the
defects should be very close to each other. When we applied a suitable bias on device,
the defects will form some localized filamentary paths, providing carrier transport
through the device, since that, an ohmic conduction will be observed, as shown in Fig.
2.9 (a). On the other hand, some carriers are trapped by defects but through the
filamentary paths, and the other carriers can transport through SiO2 thin film without
any influence by defects, as a result, it shows a transport property of SCLC.
According to the previous analyses, we suggest the devices with as-deposited and
RTA at 600oC exhibit a mixing property by SCLC and ohmic conduction. However,
the device with RTA at 800
causes a significant increase on the average distance of defects. Hence, the carriers
trapped in defects couldn’
property, as shown in Fig. 2.
Fig. 2.9: Paths of carrier transport for as
path1: conductive filaments, and (b) path2: SCLC
(b) (a)
the device with RTA at 800oC is more condensed and contains a fewer defects, it
significant increase on the average distance of defects. Hence, the carriers
’t tunnel through defects, and then, it exhibits a pure SCLC
property, as shown in Fig. 2.10.
of carrier transport for as-deposited and RTA 600oC treated samples: (a)
path1: conductive filaments, and (b) path2: SCLC
C is more condensed and contains a fewer defects, it
significant increase on the average distance of defects. Hence, the carriers
t tunnel through defects, and then, it exhibits a pure SCLC
treated samples: (a)
Fig. 2.10: Depiction of Mechanisms of carrier transport
for RTA 800oC treated sample
To elucidate the results of curve fitting of
samples and the proposed mechanisms,
It depicts that the flat band voltage (V
RTA temperature, meaning that, the total defects in SiO
increasing RTA temperature and the quality of SiO
treatment. Such results are
carrier transport mechanisms
33
Mechanisms of carrier transport in the high conductance state
treated sample.
To elucidate the results of curve fitting of the high conductance state
proposed mechanisms, the C-V characteristics are shown in Fig. 2.1
the flat band voltage (VFB) shifts from about -7V to -1V
, meaning that, the total defects in SiO2 thin film decrease with
increasing RTA temperature and the quality of SiO2 thin film is improved by RTA
are well corresponding to the previous suggestion about
mechanisms under various RTA conditions.
in the high conductance state
high conductance states in different
are shown in Fig. 2.11.
with increasing
thin film decrease with
improved by RTA
the previous suggestion about the
-8 -6 -4 -2 0 0.0
0.2 0.4 0.6 0.8 1.0
C/C max
Voltage (V) as-deposited
RTA 600oC RTA800oC
Fig. 2.11: C-V characteristics of Ag/SiO2/p-Si/Au structure of the as-deposited, RTA
600oC, and RTA 800oC treatments.
Furthermore, the low conductance currents of devices with various RTA
cinditions are fitted with Shottky emission model in log (I) versus E1/2 plots,
respectively. As shown in Fig. 2.12, a linear relationship is observed, meaning that,
the carrier injection of the low conductance currents is limited. Unsurprising fitting
results of low conductance currents are obtained due to the existence of a large barrier
height between silver and SiO2 thin film.
35
200 300 400 500 600 -9.8
-9.6 -9.4 -9.2
Log (I)
E1/2 Experimental Data Linear Fit
Fig. 2.12: Fitting of the I-V curve of the low conductance state of Al/SiO2/p+-Si
structure under different RTA conditions in a log (I) - E1/2 plot: (a) as-deposited,
(b) RTA 600oC, and (c) RTA 800oC.
RTA 800
oC
(c)
37
2.4. Summary
The RRAM device performances are list in Table 2.6. The memory properties of
Ag/SiO2/p+-Si structure with different RTA conditions are investigated and the RTA
800oC device shows the better performance. Moreover, the transition of mechanism in
the high conductance state is also proposed and discussed in this study.
Table 2.6: The performance of Ag/SiO2/p+-Si structure under different RTA conditions
SiO2
(100nm)
ON/OFF
Ratio
Retention
Time
Cycles
Transition
Voltage
Threshold
Voltage
As-deposited 105 Over 5000s 80 ~2.5V 4V
RTA (600OC) 105 Over 5000s 90 ~3V 4V
RTA (800oC) 106 Over 5000s 280 ~4V 4.5V
Chapter 3. Organic RRAM Using Metal Oxide
3.1. Introduction
In this chapter, we fabricate two different structures of organic RRAM. One of
them is Al/AlOx/Alq3/n+-Si bi-layer structure, and the other one is
Al/Alq3/MoO3/Alq3/p+-Si tri-layer structure (sandwich structure). Both devices of
bi-layer and tri-layer structure can achieve high on/off current ratio about six orders
and four orders in magnitude, respectively. At first, we propose a simpler device
structure exhibiting the high on/off current ratio than tri-layer structure. Therefore, the
Al/AlOx/Alq3/n+-Si bi-layer structure is fabricated. However, the deposition of AlOx
needs a high temperature process, and we deposit AlOx by e-gun system in this work.
In addition, this bi-layer structure is subjected to cycling problem which is that device
can’t be written and erased for many times. Therefore, to demonstrate an organic
RRAM with low temperature process fabrication for application of electronic
products, we fabricate Al/Alq3/MoO3/Alq3/p+-Si tri-layer structure to manifest this
ideal. Moreover, we investigate the electrical properties and the electrode effect on
Al/Alq3/MoO3/Alq3/p+-Si device.
3.2. Fabrication of the Organic RRAM 3.2.1. Al/AlO
x/Alq
3The device structure of the organic
bi-layer structure interposed between anode and cathode in this study
3.1 (a). First, n+-type silicon substrate
process. Then, tris-(8-hydroxyquinoline) aluminum (Alq
is given in Fig. 3.1 (b),
vacuum below 3x10-6 torr
the Alq3 thin film are about
aluminum oxide (AlOx) with
evaporation at pressure below 4x10
Al thin film is evaporated through metal mask with 2mm x 2mm square pat
devices as top electrode.
Fabrication of the Organic RRAM
3
/n
+-Si bi-layer structure
The device structure of the organic RRAM consisting of organic/metal
layer structure interposed between anode and cathode in this study i
type silicon substrate is cleaned according to standard RCA clean
hydroxyquinoline) aluminum (Alq3), whose structural formula
is evaporated onto cleaned n+-type silicon substrate
torr at room temperature. The deposition rate and thickness of
about 0.1nm/s and 45nm, respectively. Afterwards, 10nm thick
with deposition rate of 0.01nm/s is deposited by e
below 4x10-6 torr at room temperature. Finally, 100nm thick
evaporated through metal mask with 2mm x 2mm square pat
The parameters of fabrication process are shown in Table
at room temperature. The deposition rate and thickness of
Afterwards, 10nm thick
s deposited by e-beam
Finally, 100nm thick
evaporated through metal mask with 2mm x 2mm square pattern onto
The parameters of fabrication process are shown in Table
Si structure. (b) Structural
Table 3.1: The parameters of fabrication process of Al/AlOx/Alq3/n+-Si device Bi-layer
structure AlOx Alq3 Al electrode
Vacuum Value 4x10-6 Torr 3x10-6 Torr 6x10-6 Torr
Thickness 10nm 45nm 100nm
Evaporation
Rate 0.01nm/s 0.1nm/s 0.2nm/s
3.2.2. Al/Alq
3/MoO
3/Alq
3/p
+-Si tri-layer structure
The organic RRAM consisted of an Alq3/ MoO3 nano-clusters/Alq3 tri-layer
structure interposed between anode and cathode is shown in Fig. 3.2 (a). First, a
p+-type silicon substrate is cleaned according to a standard RCA clean process. A 50
nm thick Alq3 thin film is evaporated onto the cleaned p+-type silicon substrate at
pressure below 3x10-6 torr at room temperature. Then, 5 nm thick MoO3, and 50 nm
thick Alq3 thin films are evaporated in sequence onto the Alq3/p+-Si. The average
deposition rate of the Alq3 thin film and that of the MoO3 layer are about 0.1nm/s and
0.01nm/s, respectively. Finally, 100nm thick Al thin film is evaporated through metal
mask with 2mm x 2mm square pattern onto Alq3/ MoO3 nano-clusters/Alq3/p+-Si as
top electrode. Furthermore, Standard device of 100nm thick Alq3 layer is also
fabricated, and device structure is shown in Fig. 3.2 (b). The parameters of fabrication
process are shown in Table 3.2.
Fig. 3.2: Schematic diagram of
Standard devices of Alq3 single layer
Table 3.2: The parameters of fabrication process of Tri-layer
The parameters of fabrication process of Al/Alq3/MoO3/Alq3
Alq3 MoO3 Alq3 A
3.3. Organic RRAM with AlO
X/Alq
3Bi-layer Structure 3.3.1. Electrical Characteristics
In our experiment, the electrical characteristics of devices are measured using a
Hewlett Packard 4156A (HP 4156A) semiconductor analyzer in ambient environment.
The n+-silicon substrate is grounded, and all bias conditions are applied to the
aluminum electrode. In addition, the scanning interval of voltage is set to 100mV per
step in sweeping mode. Fig. 3.3 shows the current-voltage (I-V) characteristics of the
fabricated device with Al/AlOx/Alq3/n+-Si Structure. First, when a negative bias from
0V to -5V is applied on the Al electrode with 100mA current compliance, the current
is in the low conductance state with a current level of 10-13~10-6A (red solid sphere
curve). As the bias is applied at about -5V, there is an abruptly increase in current.
Then the current of the device keeps at high conductance state with a current
compliance (100mA) for the applied voltage above -5V (red solid sphere curve). This
device undergoes a resistive switching from low conductance state to high
device undergoes a resistive switching from low conductance state to high