Chapter 4 Three-Stage
4.2 N -net Fault Generation
The candidate list extracted from the first stage only collects the net-fault candidates la-beled with weights as the capability of correctly explaining EPOs under one failing pattern.
In the second stage, we further explore the multiplets of net faults that can fully explain all EPOs under all failing patterns simultaneously. Note that a multiplet of k net faults is termed a N -net fault hereafter.
The weight assignment for each candidate now takes into play and transforms the search of combinations of net faults into a BIP problem. For example, given three EPOs under one failing pattern with the candidate list L1, L2 and L3 extracted from the first stage:
L1 = {A, B, C, E} for EP O1
L2 = {B, E} for EP O2
L3 = {A, D} for EP O3
where A, B, C, D and E are nets of the circuit.
To further decide the size N and the set of N -net faults that can fully explain all EPOs, the corresponding BIP problem can be expressed into:
nA+ nB+ nC+ nE ≥ 1 nB+ nE ≥ 1 nA+ nD ≥ 1
where all net variables, nA, nB, nC, nD and nE, are binary and represent if an open occurs on net A, B, C, D and E, respectively. Besides, another constraint equation denoting the assumption for the size of N is also added as follows.
nA+ nB+ nC+ nD + nE = N
The above equation enforces that exact N opens can occur on net A to net E simultane-ously.
The BIP problem is solvable and has ate least one N -net fault if some of net variables are 1. These variables jointly form the multiplet of a fault that can correctly explain EPOs under all failing patterns. The ILP solver starts to find solutions from N = 1. If no feasible solution can be found, N increments by 1 until one solution is found. For the example in Fig. 4.2, no multiplet of N = 1 can be found and hence the ILP solver steps to N = 2. As result, four 2-net faults, (A, B), (A, E), (B, D) and (D, E) are found.
To further eliminate the faults that cannot perfectly explain all failing patterns, the weights of the candidates are added as the additional constraint equations during the BIP solving. Therefore, given the set S of N -net faults for all EPOs, the BIP problem can be updated as follows:
where each EPO under one failing pattern corresponds to one constraint equation repre-sented by (4.1). After applying the ILP solver, all N -net faults that can correctly explaining all failing patterns are reported. Note that repeated constraints are first removed from the constraint equations to reduce the runtime of the solution generation.
For example, according to the result of path tracing in Fig. 4.2, the boundary inequality equation for such pattern can be expressed into:
wAnA+ wBnB+ wCnC + wDnD+ wEnE + wFnF + wGnG+ wHnH ≥ 1
where nA, nB, nC, nD, nE, nF, nG, nH are all binary and and wA = 0.25, wB = 0.5, wC = 0.75, wD = 0.25, wE = 0.75, wF = 0.5, wG = 0.5 and wH = 1. More inequality equations can be added if other failing patterns are provided. At last, the equation denoting the size N of fault multiplets is also added:
nA+ nB+ nC+ nD+ nE + nF + nG+ nH = N
where exact N opens can occur among net A, B, C, D, E, F , G and H under all failing patterns.
These equations and weight assignments effectively limit the total number of solutions reported by the ILP solver. However, when reconvergences of multiple faults occurs in the circuit with respect to one failing pattern, the N -net fault found by the ILP solver may no longer correctly explain the reconvergent scenario. To take Fig. 4.2 for example, based on the previous constraint, (B, E) has the weighted sum 1.75 and can be reported as one 2-net faults by the ILP solver. However, under the failing pattern, an EPO occurring on net H depends on the propagation of multiple faulty values through the nets connecting inputs of gate 3 and gate 5. opens on (B, E) fails to create a faulty value on net D connecting the input of gate 3 and thus no fault can be propagated to net F and net H will not be one EPO.
To avoid generating such redundant faults, constraints called fault-propagation trees (f.p.t.) are further added for better guiding the BIP solving.
Definition: A fault-propagation tree tij is a tree for traces of signal propagataions and tra-verses backwards in the circuit topology under one failing pattern. Its root locates the net j connecting the input of a controlling-reconvergent gate i and each of its leaves lo-cates a PI or a net connecting the output of another controlling-reconvergent gate. Here a controlling-reconvergentgate denotes the gate with multiple inputs of simultaneously con-trolling values under the pattern.
Fault-propagation trees are described as individual constraints and each can be formulated into:
X
nk∈tij
nk ≤ N − 1 (4.3)
where net k is one net of the fault-propagation tree tij. Note that if tij consists of only one net, the constraint is of no use and need not to be added in the BIP problem.
Each of the above constraints means that at most (N − 1) defects can occur in tij and leaves one defect in another fault-propagation tree of gate i. To take Fig. 4.2 for exam-ple again, gate 5 is one controlling-reconvergent gate and faulty values need to propagate through both net F and net G to result in an EPO on net H. Therefore, path tracing ends up with finding constraints for t5F and t5G. In Fig. 4.3(a), since gate 3 is also one controlling-reconvergent gate, the constraint for t5F with only net F need not to be generated but two following constraints for t3D and t3E are added accordingly. In Fig. 4.3(c), path tracing finds net B, C, E and G, for t5G in a backward manner. As result, the equations for all f.p.t.
constraints are formulated as:
nA+ nD ≤ N − 1 nC + nE ≤ N − 1 nB+ nC + nE + nG ≤ N − 1
After adding these b.f.t. constraints, redundant faults such as {B, E} will not be reported by the ILP solver.
Considering the physical layout, each net in one N -net fault may consist of multiple segments and thus the size of N -segment faults can grow exponentially. For example, if a 3-net fault {A, B, C} that can be physically divided into segment set {A1, A2, A3}, {B1, B2} and {C1, C2, C3}, respectively, the total number of 3-segment faults corresponding to this fault is 3 × 2 × 3 = 18. To avoid the exponential growth on the size of N -segment faults, a X-inject-and-evaluate approach is first applied in step 1 and logically prune the false cases of N -net faults.
Symbolic X simulation is a common technique used in fault diagnosis and our X-inject-and-evaluate approach can be viewed as an extension of this technique. X’s are assigned on each net in one N -net fault and propagate towards the outputs simultaneously.
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Figure 4.3: Path tracing of fault-propagation trees
If X’s cannot be observed at all EPOs under one failing pattern, then this N -net fault is a false case and should be removed. Fig. 4.4 illustrates two examples for the X-inject-and-evaluate approach. In Fig. 4.4(a), suppose that 2-net fault (E,G) is the target. After X’s are injected on E and G, one X is blocked at gate 3 due to the controlling-value side-input connecting D. Therefore, X cannot be observed on the only EPO (net H) and thus (E,G) is removed. In Figure 4.4(b), X’s are injected on B and F and can successfully result in one X on net H. Therefore, 2-net fault (B,F ) is kept.
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Figure 4.4: Two examples for X-inject-and-evaluate