Nanocrystal nonvolatile memories first introduced in the early 1990s. IBM researchers first proposed flash memory with a granular floating gate made out of silicon nanocrystals [1.12]. Figure1-5 illustrates Nanocrystal nonvolatile memory device structures. In a nanocrystal NVM device, charge is not stored on a continuous FG poly-Si layer, but instead on a layer of discrete, mutually isolated, crystalline nanocrystals or dots. Each dot will typically store only a handful of electrons;
collectively the charges stored in these dots control the channel conductivity of the memory transistor. The charges loss through lateral paths in nanocrystal-based memory devices can be suppressed by the oxide isolation between nanocrystals, these devices exhibited superior charge storage characteristics compared with conventional floating-gate memory devices. All stored charges can’t be lost through the few leaky paths since the charges are stored in distributed nano-dots.
As compared to conventional stacked gate NVSM devices, nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing nonvolatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages
Due to the less drain to FG coupling, nanocrystal memories suffer less from drain induced barrier lowering (DIBL). One way to exploit this advantage is to use a higher drain bias during the read operation, thus improving memory access time [1.14]. There is other particular importance as the low capacitive coupling between the external control gate and the nanocrystal charge storage layer. This does not only results in higher operating voltages, thus offsetting the benefits of the thinner tunnel oxide, but also removes an important design parameter (the coupling ratio) typically used to optimize the performance and reliability tradeoff.
Unlike volume distributed charge traps (ex: nitride in SONOS NVM), nanocrystals be deposited in a two-dimensional layer at a fixed distance from the channel separated by a thin tunnel oxide. By limiting nanocrystals deposition to just one layer and adjusting the thickness of the top blocking dielectric, charge leakages to the control gate from the storage nodes can be effectively prevented.
Moreover, in optimizing NVM devices, the approach which is the focus of this study is to engineer the depth of the potential well at the storage nodes. It is said that creating an asymmetrical barrier between the substrate and the storage nodes, i.e., a small barrier for writing and a large barrier for retention. This can be achieved if the storage nodes are made of metal nanocrystals. The major advantages of metal nanocrystals over their semiconductor counterparts include higher density of states around the Fermi level, stronger coupling with the conduction channel, a wide range of available work functions, and smaller energy perturbation due to carrier confinement.
Nanocrystal memories have been presented in the mid-nineties as a possible alternative to conventional FG NVMs devices, by allowing a further decrease in the tunnel oxide thickness. Research in this area has focused on the development of
nanocrystal-based storage layers in actual memory devices. Promising device results have been presented such as demonstrating low-voltage operation for comparable threshold voltage windows. In spite of these results, it is unclear whether nanocrystal memories will ever see commercialization. In order for that to happen, the uniformity of the nanocrystals needs to be improved, and the claimed benefits need to be more unambiguously substantiated.
1.2 Motivation
The Semiconductor Industry Association (SIA) International Technology Roadmap for Semiconductors (ITRS) indicates the difficult challenge, beyond the year 2005, for nonvolatile semiconductor memories is to achieve reliable, low-power, low-voltage performance [1.15]. For nonvolatile flash memories, two limitations encountered at the present time are: (1) the limited potential for continued scaling of the device structure. This scaling limitation stems from the extreme requirements put on the tunnel oxide layer. In order to get balance between program/erase speed and retention time, there is a trade-off between speed and reliability to get the optimal tunnel oxide thickness. (2) the quality and strength of tunnel oxide (or tunnel dielectric) after plenty of program/erase cycles. Once a leaky path has been created in tunnel oxide, all the charges stored in the floating gate will be lost. Therefore, the
In this thesis, we have fabricated tungsten (W) nanocrystals nonvolatile memory device. A thin tungsten silicide (W5Si3) layer was deposited on tunnel oxide layer first.
The following oxidation was performed in furnace system. The W element tends to segregate downward and precipitate on the tunnel oxide after thermal oxidation. In addition, the silicon element is oxidized into silicon dioxide surrounded tungsten nanocrystals. Also, the carrier gas, such as O2 and N2, were also added as the tungsten silicide deposition. The memory effect and the electrical reliability for W nanocrystals surrounded in different dielectric were also investigated in this study. In addition, the formation mechanism of W nanocrystals with additional silicon oxide capped on tungsten silicide was also investigated. The thicker silicon oxide can effectively control the thermal oxidation condition and prevent thin film degradation. However, the overall oxidation cause the memory window reduction and the electrical characteristics degradation, resulted from the partially oxidation of W nanocrystal to metal-incorporated dielectric. By contrast, we also demonstrated the structure that deposited the charge trapping layer by co-sputtered W and dielectric material as SiO2 or Si3N4 to directly form the W nanocrystal embedded in dielectrics. Besides, the W and Si directly deposited by co-sputtered to adjust the two elements contained ratio had investigated as well in this study. Furthermore, the memory effect and electrical characteristics for germanium (Ge) element incorporated W nanocrystal memory were also discussed in this study.