Chapter 4 Conclusion
4.2 Negative Bias Temperature Instability
During NBTI stress, the recovery phenomenon is related to hole de-trapping due to a lower applied gate voltage, to the waiting time (tw) between the stress and the IDS-VGS characterization, and to the stress interruption. The recovery phenomenon is very critical for NBTI characterization and using the actual methodology requires special care to avoid underestimation of the ΔVT. In order to improve the characterization of NBTI gradation, the selection of the applied gate voltage and stress interruption is very significant, and the waiting time for measurement is a critical element.
After NBTI stress, the threshold voltage, subthreshold swing, field-effect mobility, and the drain current of the LTPS TFTs degrade. The NBTI can be apparently seen thermally and electrically enhanced from the results we discussed above. The grain boundaries trap-state generation must be considered to explain the NBTI degradation mechanism for LTPS TFTs due to the grain boundaries in the channel region. The extracted activation energy is about 0.07eV, just the temperature enough to break the Si-H bonds, which is the significant element in NBTI degrade mechanism. Also, NBTI leads to the interface trap states generation owning to the bond broken at the poly-Si/SiO2 interface. In summary, the NBTI degradation in LTPS TFTs is caused by the generation of fixed oxide charges, interface trap states, and grain boundary trap states, and a model is proposed and verified by the experimental results.
In the channel length effect, the degradation degree is decreased with the increasing channel length, and in the channel width effect, there is no variation led by the changing width. The results described above are different from the previous reports in MOSFETs. At this aspect, we don’t find the proper degradation mechanism to explain the phenomenon up to now and we need to check the results once again.
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Chapter 2 Fabrication and Characterization
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Figures
Fig. 1-2-1 PMOS Transistor.
(a)
(b)
Fig. 1-2-2 Band diagrams of the Si substrate of a PMOS device showing the occupancy of interface traps and the various charge polarities for a p-substrate with (a) negative interface trap charge at flatband and (b) positive interface trap charge at inversion.
Fig. 1-2-3 Schematic representation of the Si/SiO2 interface, showing the dynamic of degradation mechanism due to the hole for negative bias temperature instability.
Fig. 2-1-1 Process scheme of lateral-growth crystallized technology.
Glass Substrate Buffer Oxide
N+ N+ Poly-Si
Gate Gate Oxide
Glass Substrate Buffer Oxide
N+ N+ Poly-Si
Gate Gate Oxide
Fig. 2-2-1 The top-gated structure that the gate overlaps the source/drain 1μm of low temperature polycrystalline N-type silicon thin film transistors manufactured by the lateral-crystallized process.
Glass Substrate Buffer Oxide
N+ N+ Poly-Si
Gate Gate Oxide
Glass Substrate Buffer Oxide
N+ N+ Poly-Si
Gate Gate Oxide
Fig. 2-2-2 The top-gated structure having the lightly doped drain (LDD) structure of low temperature polycrystalline N-type silicon thin film transistors produced the lateral-crystallized process.
3.5μm
Fig. 2-2-3 The top view of a high-resolution scanning electron microscopy (SEM) image of lateral-crystallized laser annealed poly-Si film. The continuous grain boundary is called the main-GB and the discontinuous and random grain boundary is named the sub-GB.
Fig. 2-2-4 Diagram of VGB-TFT, NGB-TFT, PGB-TFT.
Glass Substrate Buffer Oxide
P+ P+ Poly-Si
Gate Gate Oxide
Glass Substrate Buffer Oxide
P+ P+ Poly-Si
Gate Gate Oxide
Fig. 2-2-5 The top-gated structure makes use of self-aligned method of low temperature polycrystalline P-type silicon thin film transistors produced by the lateral-growth crystallized process.
Fig. 2-3-1 Illustration of the Cryogenics System.
Probe switch
Thermal controller I-V measurement
connect
TPO 315A
E5250A 4284A C-V measurement
4156C
connect
Fig. 2-3-2 I-V/C-V instruments set up in the laboratory.
Glass Substrate
Fig. 2-3-3 The stress setup of the low temperature polycrystalline silicon thin film transistors (the gate was given a constant bias and the drain and the source were grounded).
Temperature=125
OC Stress Bias V
G= -30V W / L = 6 / 6
1/(V
GS-V
FB)
2(V
-2)
0.004 0.005 0.006 0.007 0.008 0.009 0.010 0.011
ln [I
DS/(V
GS-V
FB)]
Vg-Id of ELA non-LDD
Gate Voltage, Vg [V]
-10 -5 0 5 10 15
Normalized Drain Current, Id [A]
0
Vg-Gm of ELA non-LDD
Gate Voltage, Vg [V] at the temperatures from -200°C to 100°C.
Fig. 3-1-2 Two types of scatterings in MOSFET devices, including impurity scattering and the phonon scattering.
Fig. 3-1-3 The ID-VG relations of the ELA non-LDD TFT at the temperatures from -200°C to 100°C, where the ID is the linear scale.
Vg- Id of ELA LDD
Gate Voltage, Vg [V]
-10 -5 0 5 10 15
Normalized drain current, Id [A]
0
Vg-Id of ELA non-LDD
Gate Voltage, Vg [V]
-10 -5 0 5 10 15
Normalized Drain Current, Id [A]
0 the temperatures from -200°C to 100°C.
Vg- Gm of ELA LDD
Vg-Gm of ELA non-LDD
Gate Voltage, Vg [V] the temperatures from -200°C to 100°C.
(a)
(b)
Fig. 3-1-6 The sheet resistances of phosphorous (a) lightly-doped and (b) heavily-doped poly-Si film at the temperatures from 50K to 300K.
(a) High Temperature
(b) Low Temperature
Fig. 3-1-7 The dynamic and number of the free carriers of the lightly-doped Si film at (a) High Temperature and (b) Low Temperature from the viewpoint of band-diagram.
Fig. 3-1-8 The LDD layers extended out the gate overlap region behave as the temperature-dependent resistors and series connecting with the gate control region.
ΔVth
- Temperature of LDD Devices
ΔVth
- Temperature of non-LDD Devices
Temperature [OC]
ΔμFE - Temperature of LDD Devices
ΔμFE
- Temperature of non-LDD Devices
Temperature [OC]
W=30, L=6, VG= -15V @ 25℃
Fig. 3-2-1 ΔVth as a function of stress time of the TFT suffered 1000sec stress at 25°C under the stress voltages VG= -15V and the removal of stress revealing the recovery phenomenon.
Fig. 3-2-2 Schematic diagram of NBTI stress setup for the p-type ELA TFT. The stress temperature was performed from 25 to 150°C, and the stress gate voltage was applied in the range of from −15 to −25V with the source and drain grounded.
Drain Voltage, V
DS[V]
Normalized D rain Current, Id [A]
10-13
Fig. 3-2-3 The (a) transfer characteristics and (b) output characteristics of the TFT before and after 1000sec NBTI stress at 125°C with the stress voltage is -25 V.
125OC
Fig. 3-2-4 Dependence of the threshold-voltage shift on the (a) stress time, (b) stress temperature, and (c) stress voltage under various stress conditions.
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 ln[I DS/(V GS-V FB)]
Fig. 3-2-5 Grain boundary trap-state density extraction of the TFT before and after 1000ecs NBTI stress at 125°C with the stress voltage of −25 V.
125OC
Fig. 3-2-6 Dependence of the grain boundary trap-state generation on the (a) stress time, (b) stress temperature, and (c) stress voltage under various stress conditions.
Gate Voltage, Vg [V]
Fig. 3-2-7 Comparison of the parameters extracted from the threshold-voltage shift and the grain boundary trap-state generation.
ΔVth [V]
Fig. 3-2-8 Correlation between the grain boundary trap-state generation and the threshold voltage shift of the LTPS TFTs after NBTI stress.
ΔVth [V]
Fig. 3-2-9 Correlation between the subthreshold swing degradation and the threshold voltage shift of the LTPS TFTs after NBTI stress.
Fig. 3-2-10 Energy band diagram of the p-channel LTPS TFT under NBTI stress.
ΔV
th- Stress Time
Stress Time [sec]
200 300 600 20003000
100 1000
ΔV th [V]
0.15 0.2 0.3 0.4 0.5 0.6
L=3um L=6um L=9um L=12um L=18um
Fig. 3-2-11 ΔVth as a function of stress time of the different length and fixed the width=6μm of ELA TFTs suffered 3000sec stress at 125°C under the stress voltages VG=-30V.
Channel Length [um]
2 4 6 8 10 12 14 16 18 20
Δ V
th[V]
0.48 0.50 0.52 0.54 0.56 0.58
Fig. 3-2-12 The relationship between the channel length and ΔVth after NBTI.
ΔV
th- Stress Time
Stress Time [sec]
200 300 600 20003000
100 1000
ΔV th [V]
0.15 0.2 0.3 0.4 0.5 0.6
W=6um W=24um W=60um W=90um W=180um
Fig. 3-2-13 ΔVth as a function of stress time of the different width and fixed the length=6μm of ELA TFTs suffered 3000sec stress at 125°C under the stress voltages VG=-30V.
Channel Width [um]
0 30 60 90 120 150 180
Δ V
th[V ]
0.50 0.52 0.54 0.56 0.58
Fig. 3-2-14 The relationship between the channel width and ΔVth after NBTI.
Tables
Table 1 The comparison of device degradation degree applied different gate voltage under NBTI stress with no stress interruption.
W=30,L=6 VG = -10V @ 100°C VG = 10 ~ -15V
Stress time(sec) VT ΔVT ΔVT percentage(%)
0 0.4623
1000 0.4477 0.0147 3.1717 VG = 2 ~ -8V
Stress time(sec) VT ΔVT ΔVT percentage(%)
0 0.4523
1000 0.4200 0.0323 7.1349
Table 2 The comparison of device degradation degree applied different gate voltage under NBTI stress with multi-step stress interruption.
W=30,L=6 VG = -10V @ 100°C VG = 10 ~ -15V
Stress time(sec) VT ΔVT ΔVT percentage(%)
0 0.4140
10 0.4118 0.0022 0.5209 500 0.4043 0.0097 2.3381 1000 0.4010 0.0130 3.1407
VG = 2 ~ -8V
Stress time(sec) VT ΔVT ΔVT percentage(%)
0 0.3941
10 0.3899 0.0042 1.0558 500 0.3762 0.0179 4.5331 1000 0.3732 0.0208 7.1349