3. Hardware and Operating System
3.3 NesC
NesC [19] means Network Embedded System C and it is an extension type of the C language. All of the TinyOS operating system, libraries and applications are written in NesC. The basic concepts for NesC are listed as below.
z Code will be generated by program compilers.
It can increase runtime efficiency and robust design, so the components are statically linked to each other via their interfaces. It provided a better code generation and static analysis and it can detect data race at compile-time.
z Component behaviors are specified in a set of interfaces.
The provided interfaces are intended to represent the functionalities that the components provide to its user. The used interfaces used the functionalities that component needs to perform its job.
z Interfaces are bidirectional:
There are two kinds of interface, “provide” and “use” interface. Provide interface means components implement a set of functions, then other components can wire to the interfaces and used these functions. Use interface means components implement a set of callback functions. The provide interface will call these callback functions when some commands had done.
For the bidirectional interface aspect:
Interface Command Event
Use Call Implement functions
Provide Implement functions Signal
Table 3-1. Relation between provide and use interface.
One example in Figure 3-3, it shows how the configuration files to wire modules together. Configuration wires modules BlinkM and SingleTimet by interface Timer and it also wires modules BlinkM and LedsC by interface Leds.
Figure 3-3. Example for wiring modules.
Chapter 4
System Architecture to Realize TDMA
In this chapter, we will introduce the components in TDMA mechanism and focus on components implementation. The goal is to design the suitable modules and use these modules to realize TDMA mechanism. The exported functions will be declared in interfaces then application layer programs can wire these modules together and use the provided functions.
4.1 System architecture
In this section, we will overview TDMA mechanism in two aspects. Fame structure is for system running time period and software components architecture is for the relation between components. There are three basic components in TDMA mechanism which includes time synchronization, slot assignment algorithm and mode selection.
4.1.1 Fame structure
The frame structure is composed of control phase and transmission phase. There are three types of periods: time synchronization period, slot assignment period and mode selection period. The overview of TDMA scheme is shown in Figure 4-1.
In control phase, each node will recognize and record its parent node then system will build up a parent-child forwarding tree. After each node has learned its parent node, system will do time synchronization (section 4.2) for each pair of parent and child nodes.
In time synchronization period, each child node will send time synchronization packets to its parent node and parent node will send back acknowledge packets with timestamp.
Then child node will depend on timestamp to calculate time offset then modifies its local time to match with parent node. When this period is completed, system will enter slot assignment period.
In slot assignment period, each mote will collect all of its one-hop and two-hop
neighbor’s information through packets exchange then node will execute slot assignment algorithm (section 4.3). After executed the algorithm, every node in the system will get its slot number. Then each node sends packet to sink with its slot number through parent-child forwarding tree. Sink will receive all the reports from each node then sink calculates cycle length by this information. Finally, sink will broadcast packets with total cycle length inside.
In transmission phase, there is mode selection period inside. Mode selection period (section 4.4) will be divided into transmission operation, receipt operation and idle operation. After control phase completed, each node got its slot number. At the beginning of each time slot, node will enter one of above operation modes. When node owns current time slot, it will enter basic transmission operation and node can transmit packets in this time slot. When one of the node’s one-hop neighbors owns current time slot, node will enter basic receipt operation and wait for receiving packets from its neighbors. When current time slot is neither owned by the node nor by its one-hop neighbors then node will enter idle mode.
At the beginning, system enters control phase and each node executes time synchronization and slot assignment algorithm. Then system enters transmission phase after system nodes have synchronized with their parent nodes and get their own time slots. In transmission phase, system nodes will transmit and receive packets under TDMA mechanism for a long period of time. After a long time, system will enter control phase again. Then nodes will re-synchronize with their parent nodes and do slot assignment algorithm again.
Figure 4-1. TDMA mechanism overview, N modes in network 4.1.2 Software components architecture
In the thesis, we do not design new MAC layer protocol and physical interface. So the TDMA mechanism is still base on the B-MAC protocol. Actually, it works as the middleware between application layer program and low-level hardware. The relation between TDMA components and TinyOS’s components is shown in Figure 4-2. TDMA module will provide several interfaces then upper application will wire them and use the related commands or events.
Time synchronization, slot assignment algorithm and mode selection components will process packets transmission, packet receipt and message exchange. So these components will connect to TinyOS transmit and receive component groups. In these groups, active message component will provide interfaces with packet transmission and receipt for upper application. CC2420 related components will control the interrupt of packets sending and receiving, switch hardware into transmit mode or receive mode, read and write data from FIFO queue, RF power and so on.
Time synchronization component will connects to timestamp component group. In this group, time component provides system time and we use it for time synchronization.
Mode selection component will connect to power management components group which will control ATmega128 in active, idle and other power saving modes. Power
management components also can turn on and turn off CC2420’s crystal oscillator. By this way, it can disable RF interface when the mote into idle mode.
TDMA
In TDMA architecture, time synchronization is an important topic because every system mote will power on at different time. Without accurate time synchronization, some motes will transmit packets at the same time. It will cause interference, packets collision and reduce the performance.
4.2.1. Overview
Our time synchronization is designed base on TPSN[8] and we have introduced the
basic concepts in section 2.2.1. At the beginning of control phase, TPSN protocol is running. Child node will synchronize system time with its parent node and it can eliminate clock offset issue between itself and parent node. Actually, there are some uncertain factors in time synchronization. In TPSN, send time, access time and receive time are important because system posts task for packet transmission and signal receive event.
In Micaz platform, Chipcon CC2420 [17] will access 802.15.4 radio packet and it connected to ATmega128 through SPI interface. Packet format is shown in Figure 4-3.
There is one pin which named “SFD” in Chipcon CC2420. SFD pin goes active when the start of frame delimiter (SFD) field in radio packet has been completely transmitted or radio packet’s SFD field in 802.15.4 [20] packet has been completely received.
For packet transmission [21], application layer program sent radio packets by posting a task. System will prepares packet header and payload then put this task into task FIFO queue. In the FIFO queue, task will be handled by sequence. It is not suitable to add timestamp in application layer. Because there must have uncertain time difference between calling system function and packet leaving radio interface. One better way is to add packet timestamp in MAC layer instead of adding it in application layer. For packet receipt, time difference still exist between packet arrived at MAC layer and application program been noticed to retrieve packet from receive buffer.
Figure 4-3. IEEE 802.15.4 packet format.
4.2.2. Implementation detail
For TPSN implementation, sink node will broadcast discovery packet in initial time. This packet contains level value and local node id. Nodes receive discovery packet
will record source node id as parent node id then re-broadcast it with increment level value by one. Nodes not receive discovery packet will broadcast request packet for getting level value. Any node receives request packet will send discovery packet to it.
For time synchronization, it is the two way packets exchange with timestamp.
During synchronization, if there is no response from parent node, child node will send synchronization packet again. If it is still no response for several times, child node will send request packet then retrieve level value and parent node again. It is important not to add timestamp in application layer. In packet transmission procedure, sending system function will prepare packets and put them into Chipcon CC2420 TXFIFO buffer through module HPLCC2420FIFOM. During packet transmission, CC2420 SFD pin will active when the packet SFD field (start of frame delimiter) has been sent. It will trigger interrupt then we have to capture current system time and add timestamp in sending packet. Above procedures are implemented in interrupt handler. For packet receipt, packets will put in CC2420 RXFIFO. During this period, SFD pin will active when the packet SFD field has been received. We also capture current system time in the interrupt handler and record it as receipt time. Figure 4-4 shows the relation between timestamp and SFD pin.
Figure 4-4. Timestamp with the SFD (a) sending packet (b) receiving packet
During code implementation, something should be noticed:
z During packet transmission period, SFD interrupt is happened. It is important to generate timestamp and add it into packet as soon as possible. Otherwise, packet had been transmitted already and packet payload will not be modified.
z In time synchronization, there are many packets with different types such as level discover, time synchronization and synchronization acknowledge packets. It is a good idea to assign different type packet with different handle ID. The handle ID can be assigned in configuration files. TinyOS will dispatch these packets to the corresponded functions and it will be easier for code implementation and debugging.
Reference to Figure 4.2, time synchronization operation uses all the components in
“Transmit and Receive components” and “TimeStamping components”.
4.3. Slot assignment algorithm
4.3.1. Overview
In control phase, each mote can get its own slot number through slot assignment algorithm. We use node ID, request packets and grant packets to do slot assignment.
Every node will maintain one-hop and mixed-hop neighbor link lists which include neighbor’s information such as node ID, node slot number and so on.
The main procedures of slot assignment algorithm as following:
z Mote X will collect its entire one-hop and two-hop neighbor’s information then build up one-hop and mix-hop neighbor link lists.
z According to mixed-hop neighbor link list, mote X will send slot request packets to all of its one-hop and two-hop neighbors.
z When mote Y received slot request packet from mote X.
If mote Y does not get its slot number yet and Y.id < X.id then mote Y will reply slot grant packet to mote X.
Otherwise, mote Y will do nothing.
z Once mote X receives all grant packets from its one-hop and two-hop neighbors then mote X will select one slot number which is not used by its one-hop and
two-hop neighbors.
z Mote X will send slot number grant packet to its one-hop and two-hop neighbors with selected slot number.
z Mote X will send packet to sink with selected slot number.
z Sink receives all of these packets from system nodes and calculates slot cycle length.
z Finally, sink will broadcast packets with slot cycle length information.
4.3.2. Implementation detail
Each node will maintain one-hop and two-hop neighbor information. Because the numbers of neighbors are uncertain so we create two link lists. One-hop neighbor link list contains node’s one-hop neighbor node id. The link list will be used by other nodes to build up mixed-hop neighbor link list. Mixed-hop neighbor link list contains node’s one hop and two hop neighbor node id and slot number. Slot assignment algorithm will use above information to calculate system nodes slot number. These two link lists are shown in Figure 4-5.
Figure 4-5. (a) One-hop neighbor link list (b) Mixed-hop neighbor link list
In this section, there are several different packet types and we list some packet types as shown in Table 4-1. The following steps show how the slot assignment works.
Packet Type Description
One hop request packet Request for node’s one-hop neighbor.
One hop reply packet
One-hop neighbor replies to request node with node id.
One hop information packet
Node broadcasts all of its one-hop neighbors node id.
Slot request packet Request for one / two-hop grant packet.
Slot grant packet Reply to request node with grant information.
Slot number grant packet
Node informs its one and two hop neighbor with selected slot number.
Slot number sink packet
Node informs sink with selected slot number.
Table 4-1. Several packet types in slot assignment
First, node X will broadcast one hop request packets with node id. All of node X’s one hop neighbor nodes will receive these request packets then send one hop reply packets to node X. Node X will build up one-hop neighbor link list by these one hop reply packets. By the same way, node X’s one-hop neighbors also build up their one-hop neighbor link list.
Second, node X will broadcast one hop information packets which contains all of its one-hop neighbor nodes id and local node id. When node Y received these packets, it will know the entire two hop nodes id. By the same way, node X also knows the entire two hop nodes id. Node X will receive many one hop information packets from its one hop neighbors and it will filter out the redundant packets then build up the mixed hop neighbor link list.
Third, node X refers its mixed hop neighbor link list and sends slot request packets to its one hop and two hop neighbors with local node id. According to slot assignment algorithm (section 4.3.1), node X’s neighbors will send slot grant packets to node X when its nodes id are small than node X’s id.
Fourth, node X received slot grant packets and it will check all of the neighbor’s
grant packets are ready or not. After all of the grant packets are received, node X will select one slot number different than its neighbors. Node X will send slot number grant packets to its entire one hop and two hop neighbors. These nodes will modify their mixed hop neighbor link list.
Fifth, node X will send slot number sink packet to sink. Sink will calculate total slot cycle length and broadcast slot cycle length information.
According to slot assignment algorithm (section 4.3.1), node with largest id will collect the entire one hop and two hop neighbor’s grant packets earlier than the other nodes. So the node with largest id will select its slot number first the smallest id node will select its slot number at the end.
One example is shown in Figure 4-6. This example explains how to build up mixed hop neighbor link list.
z Node 1: One hop neighbor link list: {2, 3, 5}
Node 2: One hop neighbor link list: {1, 3, 4}
z Node 1: Broadcast one hop information packet: {1, 2, 3, 5}
Node 2: Broadcast one hop information packet: {2, 1, 3, 4}
z Node 1: Received one hop information packet from node 2.
Builds up mixed neighbor link list: {2, 3, 4, 5}
Node 2: Received one hop information packet from node 1.
Builds up mixed neighbor link list: {1, 3, 4, 5}
z Node 1: Knows node 4 is two-hop neighbor now. Node 1 will send slot request packet to node 4 later.
Node 2: Knows node 5 is two-hop neighbor now. Node 2 will send slot request packet to node 5 later.
Figure 4-6. Build up mixed hop neighbor link list.
In the real environment, radio interference and packet loss can not be avoided, so something should be noticed:
z When mote X broadcasts one hop request packet and it receives over two one hop reply packets from mote Y. Mote X will add mote Y in one-hop neighbor link list.
z Mote X sends slot request packet to all of its one-hop and two-hop neighbors, when packet timeout happened it will send request packet again.
Reference to Figure 4.2, slot assignment algorithm uses all the components in “Transmit and Receive components”.
4.4. Mode selection mechanism
After each node doing time synchronization with its parent node and getting its slot number (section 4.3), system will enter transmission phase. There are three operations in mode selection mechanism, transmission, receipt operation and idle operation.
In mode selection phase, mote will wake up in the beginning of each time slot period. In this moment, mote will check some conditions and enter one of the following operations.
z Transmission operation: Mote owns current time slot, it means the mote has the possibility to transmit packets.
z Receipt operation: One of mote’s one hop neighbor nodes owns current time slot, it means the mote has the possibility to receive packet.
z Idle operation: None of above conditions then mote enters power saving mode.
Figure 4-7. Mode selection mechanism
We will explain how to implement TDMA time slot. Each mote manipulates its hardware timer counter and the corresponding interrupt will be triggered when the timer counter is overflow. Timer interrupt handler will trigger the prepared callback function.
With above relations, timer interrupt will cut time axis into several time slices. Motes will do mode selection in the interrupt handler function.
Figure 4-8. Time slot and interrupt
In MICAz, ATmega128L [16] provides four hardware timers. Timer0 is used by system timer and Timer1 is used by Chipcon CC2420 [17] radio stack. Timer3 is a 16 bit timer, it will be better than 8 bit Timer2 in time resolution.
Before hardware timer works properly, there are some configurations and initial
procedures must be done. We list the main procedures as below.
Step 1: Disable Timer3 output compare match interrupt.
Step 2: Select timer to Clear Timer on Compare match (CTC) mode.
Step 3: Select clock prescaler value.
Step 4: Select output compare register.
Step 5: Assign default values for output compare register and Timer3 counter register.
Step 6: Prepare interrupt handler function.
Step 7: Enable Timer3 output compare match interrupt.
The relations between application layer program and Timer3 components are shown in Figure 4-9.
z Timer3M and HPLClock3 are components for implementation.
z Configuration Timer3C wired components MainC and Timer3M.
z Configuration Clock3C wired components Timer3M and HPLClock3.
z In HPLClock3, it will handle the timer and interrupt ISR by accessing the register value in ATmega128.
Both of transmission operation and receipt operations will do packets communication.
There are something should be noticed as below.
There are something should be noticed as below.