Chapter 1 Introduction
1.3 Organization
In this thesis, chapter 2 describes how to realize the proposed I/Q calibration generator and LO generation architecture. The detail operation theory and improved performance are presented, and verified by chip implementation. Chapter 3 describes the direct-conversion front-end receiver design. The components employed in the receiver, such as LNA (low noise amplifier), down-conversion mixer, VCO, are also discussed. Chapter 4 describes the implementation of a frequency synthesizer chip with low phase noise and low reference spur. The design flow and performance optimum are presented. Finally, Chapter 5 describes the conclusions and future works.
Chapter 2
Quadrature LO Generator with I/Q Mismatch Calibration
Direct down-conversion from 5GHz requires quadrature LO generation at the RF carrier frequency, which may result in large gain and phase mismatches. Other significant problems include sensitivity to flicker noise and pulling of the VCO by the external or on-chip PA. In addition to these architecture-related nonidealities, higher order QAM-OFDM modulation requires tightly matched I/Q signal path on both transmit and receive side to avoid degradation of the overall EVM.
2.1
Phase-calibrated LO Generator
In this section, we present the phase-calibrated LO generator. In our frequency planning, a “fractional VCO” is adopted in which the desired RF frequency is 1.5 times higher than the VCO frequency [5]. Fig 2.1 reports an LO generation scheme that consists of a VCO operating at two-thirds of the LO frequency and a divide-by-2 divider generating quadrature outputs at one-third LO frequency. Besides, additional phase-calibrated LO generators are employed and combined with up-conversion mixers in LO I/Q path for phase error calibration.
Fig. 2.1 Calibrated LO generator architecture
As the VCO operates at two-thirds of the LO frequency (3.5GHz), this scheme can effectively avoid pulling and reduce LO-RF interaction. However, the generated LO signal has strong lower sideband at one-third of LO frequency, which is roughly 1.75GHz, a highly populated frequency band where high-power transmitters exist. To suppress the lower side band image at the LO I/Q output, the up conversion mixer utilizes LC tanks as the output load.
Assume vector I and Q are not orthogonal, as is illustrated in Fig 2.2, a modified quadrature phase Q’ can be generated by summing up Q with a compensated vector –I.
Once the polarity and weighting factor of the compensation can be digitally controlled, a precise I/Q signal can be generated by eliminating their phase error. Fig 2.3 depicts the phase-calibrated LO generator, which performs as an up conversion mixer with phase compensation capability. The divider output I/Q signals at 1/3 fLO are applied to the transconductance stages (M1-M6) of the mixer, while the VCO output at 1/3 fLO are applied to commutating stages (M7-M10) of the mixer. The vector compensation is achieved by I/Q phase current mixing.
I ) 2 ( -I ) 1 (
I α a
α =
Fig. 2.2 Phase compensation concept
Fig. 2.3 Phase-calibrated LO generator
Assume
The compensated quadrature vector (Q’) can be derived as
Here 1 and 2 are controlled by 4 bits DAC A and B respectively. Thus the
Q
I
Q'
=α
+β
polarity and magnitude of the compensated current can be digitally programmed to null out the phase error.
2.2
Phase Calibration Verification
To evaluate the performance of the calibration LO I/Q generator, we must measure the phase and gain errors. But it is very hard to measure those parameters of quadrature phase outputs at such high frequency. To get information about phase error, we can use the image rejection down-conversion mixers to mix down LO I/Q signals with accurate quadrature RF I/Q signals and measure the image rejection ratio (IRR).
Specific relations exist between gain error, phase error, and image rejection ratio.
Fig. 2.4 Phase compensation concept
Assume we generate and inject signals at two frequencies: LO, RF respectively, then mix them together. Parameter represents the magnitude error of LO I/Q signals and represents phase error of them.
: (2.1). Inversely, when we mix –RFI and RFQ with LOI and LOQ respectively, we get down-conversion image signal at frequency of RF - RF, as indicated in equation (2.2). However, up-conversion signals at frequency of RF + RF after mixing will be filtered by the band-limited circuits, such as down conversion mixers, output buffers, and low pass filters. Image rejection ratio (IRR) is magnitude ratio between them, which is listed in equation (2.3).
θ
By using MATLAB, we can show relations between gain error, phase error, and image rejection ratio in Fig 2.5 and Fig 2.6.
wanted signal
image signal
Fig. 2.5 Relations between IRR, phase error, and magnitude error
Fig. 2.6 Relations between IRR, phase error, and magnitude error (3D)
From IEEE 802.11a specification, we get that EVM has to be less than -25dB for good data constellations. From hand calculation, EVM can be expressed as:
dB Log
EVM 25
2
cos 2
1 ) 1
20 ( +
2+ − × < −
≈ ε ε θ
(2.4)According to equation (2.3) and (2.4), it reveals that IRR has to be greater than 28dB to achieve specification. If I/Q mismatch of 0.8˚ and 0.2dB can be achieved by our proposed phase -calibrated mechanism, IRR will be greater than 37.4dB and EVM will be less than -34.3dB. By MATLAB, we can show relations between magnitude error, phase error, and EVM as shown in Fig 2.7.
Fig. 2.7 Relations between EVM, phase error, and magnitude error
In order to determine the maximum phase compensation, Monte Carlo simulations have been employed for analyzing the maximum I/Q phase error from component mismatches. As shown in Fig 2.8, Monte Carlo simulations (50 times) using Gaussian distribution show that maximum phase error would achieve about 2.2˚
in the presence of 10% and 6-sigma device channel length mismatches. Furthermore, as shown in Fig 2.9, under more serious conditions, Monte Carlo simulations ( 50 times) using uniform distribution show that maximum phase error would achieve about 5.9˚ in the presence of 10% and 6-sigma device channel length mismatches.
Thus, according to mention before, the calibrated LO I/Q generators have to be designed to have capability of compensating maximum phase error about 6˚. In our phase compensation plan, I/Q phase error less than 10˚ can be compensated to less than 0.8˚.
Fig. 2.8 Monte Carlo simulations using Gaussian distribution
Fig. 2.9 Monte Carlo simulations using uniform distribution
The DAC_A and DAC_B in Fig 2.3 are current-mode D/A converters and controlled by 4-bit binary-weighted current sources, as shown in Fig 2.10. The currents through DAC_A and DAC_B are proportional to their bit numbers respectively and total current through them are constant. In this work, the sum of bit numbers of DAC_A and DAC_B is a constant value, 16. By assigning bit number of DAC_A and DAC_B, I/Q phase compensation polarity and magnitude can be digitally controlled. As I/Q phase error is zero, DAC_A and DAC_B have the same current and
Fig. 2.10 Monte Carlo simulations using Gaussian function
bit number, 8, so phase-I signals for compensation in Fig. 2.3 are canceled through cross couple pairs, M1-M4. And from roughly hand calculation and simulation result, current ratio under minimum DAC control is ( 2I / 65I ), which results in I/Q phase variation about 1.54. And current ratio under maximum DAC control is ( 15I / 65I ) , which results in I/Q phase variation about 9.58. I/Q phase change versus DAC control step (the difference between bit number of DAC_A and DAC_B) is shown in Fig. 2.11.
Fig. 2.11 I/Q phase change versus DAC control step
2.3
Gain-calibrated Down-conversion Mixer
To compensate the gain error at signal I/Q path, receiver frond-end (LNA + Mixer) is designed to provide fine gain control in I/Q paths conversion gain. However, the gain of LNA is the same for signal I/Q path. Therefore, the down-conversion mixers at signal I/Q path are suit to provide this function. The simplest way is to make changes in resistor load of mixers. Fig 2.12 shows that resistor load adjusted by switching sw4 and sw5. As sw4 and sw5 turn on, resistor load is “R + 5R”. As sw4
turns off and sw5 turns on (or inversely), resistor load is “(5R/4) + 5R”, mixer gain increases 0.4dB. As sw4 and sw5 turn off, resistor load is “(5R/3) + 5R”, mixer gain increases about 0.7dB. Therefore, if signal I/Q path exists gain error less than 1dB, after gain error calibration, gain error will be less than 0.2dB.
Fig. 2.12 Resistor Load is fine controlled by sw4 and sw5
2.4
Circuit Realizations
In this section, we will discuss other block designs in Fig 2.4, such as complementary VCO, divide-by-2 divider, and source couple pair adder.
2.4.1 Complementary VCO
In this work, our VCO design adopted differential complementary cross-coupled LC oscillator architecture, as shown in Fig 2.13. Symmetric inductor and accumulation-mode varactor is used for inductor and capacitance of VCO.
Complementary cross-coupled architecture saves more power than only nmos or pmos cross-coupled architecture because negative resistance becomes double. Also, its phase noise performance can be further improved by means of the complementary architecture thanks to symmetric output waveform [9].
Fig 2.13 Complementary cross-coupled VCO
2.4.2 Divide-by-2 divider
Fig 2.14 shows a divide-by-two divider schematic utilized to generate the quadrature LO signals. The circuit is realized as two master-slave D flip-flops configured in a negative feedback loop. Each flip-flop consists of a differential amplifier followed by a regenerative cross coupled pair. Thus dividing signals with I/Q phases can be derived at the divider outputs. The detailed schematic of MS-D-FF is shown in Fig 2.15. Typical device mismatches result in phase imbalances as large as 5 [10].
Fig. 2.14 Divide-by-2 divider configuration
Fig. 2.15 Divide-by-2 divider
2.4.3 Source Couple Pair Adder
Fig 2.16 shows a source couple pair adder schematic. Since RF I/Q signals mix with LO I/Q signals respectively, then down convert to baseband signals (150k ~ 8.3MHz) and added up through source couple pair adder. If down-conversion signals were wanted signals, they would be sum up. However, if down-conversion signals were image signals, they would be canceled out.
Fig. 2.16 Source couple pair adder
2.5
Simulation result
Transient response of each circuit block is shown in the following. The simulation results of VCO differential output waveforms are shown in Fig 2.17.
Quadrature outputs of divide-by-2 divider are shown in Fig 2.18. The mixing up-conversion quadrature LO waveforms through phase-calibrated LO generator are shown in Fig 2.19. Fig 2.20 shows that simulation result of down-conversion wanted signal at 20MHz. On the other hand, Fig 2.21 shows that simulation result of down-conversion image signal at 20MHz.
Fig. 2.17 VCO differential output waveforms
Fig. 2.18 Quadrature outputs of divide-by-2 divider
Fig. 2.19 Quadrature LO waveforms
Fig. 2.20 Down-conversion wanted signal
Fig. 2.21 Down-conversion image signal
The spectrum of quadrature outputs of divide-by-2 divider is shown in Fig 2.22.
As can be seen in Fig 2.21, LO signal power at 5.25GHz is higher than that of lower side band about 27dB. Fig 2.23 shows that spectrum of down-conversion wanted signal in Fig 2.20 and Fig 2.24 shows that spectrum of down-conversion image signal in Fig 2.21. As can be seen in Fig 2.23 and Fig 2.24, the simulated IRR is greater than 50dB under I/Q matching situation. In Table 2.1, it lists the performance summary of quadrature LO generator with I/Q mismatch calibration.
Fig. 2.22 Spectrum of quadrature outputs of divide-by-2 divider
Fig. 2.23 Spectrum of down-conversion wanted signal
Fig. 2.24 Spectrum of down-conversion image signal
Table 2.1 Performance summary
Technology TSMC 0.18 um CMOS
Supply Voltage 1.8 V
I/Q phase error < 0.8
I/Q gain error < 0.2dB
Max. phase compensation 9.58
IRR > 37.4 dB
VCO tuning range 3.18GHz ~ 3.74GHz
VCO 3.56 mW
I/Q divider 5.94 mW LO generator 5.86 mW
Mixer 9.42 mW
Adder 20.63 mW
Power Consumptions
Overall 45.41 mW
2.6
Measurements
A Quadrature LO generator with I/Q mismatch calibration is designed and fabricated in TSMC 0.18m technology. This section includes chip photograph, measurement setup and experimental results. Measured performances are taken into discussions.
2.6.1 Measurement Setup
Dies for measurement are bare and required to be bonded on PCB board.
Packages are excluded for complicated parasites. The chip microphotograph and bonding board for measurement test are shown in Fig 2.25 and Fig 2.26. The chip need quadrature RF inputs, and thereby quadrature generator is necessary.
Fig. 2.25 Chip microphotograph of quadrature LO generator
Fig. 2.26 Bonding board
DC board is used to provide the supply voltage, bias, and ground for bonding board. After plugging the DC board with the bonding board, test platform is completed as shown in Fig 2.27. SMD bypass capacitors are connected on the bonding board to filter out the high-frequency noise from supply and external components. The transformers with module number ADT1-6T are made by Mini-circuits. Signal attenuations caused by the matching network, transmission line,
Fig. 2.27 Plugging DC board with bonding board
coaxial line and transformer network are measured and compensated back to measurement results.
In Fig 2.28, it shows the measurement setup diagram of quadrature phase-calibrated LO generator with image rejection mixers. Input signal is provided from external signal generator and quadrature signals are generated through quadrature hybrid. By adjusting frequency control voltage of the VCO, we can down convert RF signals to frequency band of 150k ~ 8.3MHz. At the output terminals, a transformer converts differential outputs to single output and feeds this output to spectrum analyzer. By spectrum analyzer, we can measure image signal and wanted signal, thus IRR can be get.
Fig. 2.28 Measurement setup diagram of quadrature phase-calibrated LO generator with image rejection mixers
2.6.2 Measurement Results
In Fig 2.28(a), it shows that photograph of quadrature hybrid. It is a four-port component. As RF signal inputs from one port, other two ports will generator RF I/Q signals at some frequency and the other port is isolated, i.e., the signal is cancelled at this port. In Fig 2.28(b), it shows that precise quadrature phase is at frequency of 5.335GHz. Fig 2.28(c), it shows that difference of S21 at 5.335GHz is about 0.7dB, a significant magnitude mismatch between port of RF_I and port of RF_Q.
Fig. 2.28 Quadrature hybrid (a) photograph (b) phase difference between port of RF_I and RFQ (c) gain error between port of RF_I and RF_Q
(a)
(b)
(c)
In Fig 2.29, it shows input matching condition at RF I/Q input ports. At frequency of 5.335GHz, I/Q input matching is similar, thus it is suitable for injecting RF test signal at 5.335GHz. In Fig 2.30, it shows operating frequency of VCO versus control voltage and reveals that desired frequency of 5.335GHz is achievable.
Fig. 2.29 I/Q port input matching
Fig. 2.30 Down-conversion signal from Q path
In Fig 2.31, it shows down-conversion signal by mixing of RFI and LOI. In Fig 2.32, it shows down-conversion signal by mixing of RFQ and LOQ. From Fig 2.31 and 2.32, it reveals that gain error about 2dB exists in I/Q path. However, our design is only able to calibrate gain error less than 1dB. This gain error exceeds our estimate.
Fig. 2.31 Down-conversion signal from I path
Fig. 2.32 Down-conversion signal from Q path
In Fig 2.33, it shows down-conversion signal is about -45.3dBm. In Fig 2.34, it shows down-conversion image is about -62.35dBm. From Fig 2.33 and 2.34, it reveals that IRR is about 17.05dB before calibration. And we can estimate that gain error is about 2dB and phase error is about 6.
Fig. 2.33 Down-conversion signal (before calibration)
Fig. 2.34 Down-conversion image (before calibration)
In Fig 2.35, it shows down-conversion signal is about -43.86dBm. In Fig 2.36, it shows down-conversion image is about -72.11dBm. From Fig 2.35 and 2.36, it reveals that IRR is about 28.25dB after calibration. And we can estimate that gain error is about 0.66dB and phase error is less than 1.
Fig. 2.35 Down-conversion signal (after calibration)
Fig. 2.36 Down-conversion image (after calibration)
In Table 2.2, it lists the performance summary of quadrature LO generator with I/Q mismatch calibration. Measured IRR is underestimated because of gain mismatch in quadrature hybrid and devices mismatch in I/Q signal path.
Table 2.2 Measured performance summary
Technology TSMC 0.18 um CMOS
Supply Voltage 1.8 V
I/Q phase error < 1
I/Q gain error 0.66dB
IRR 28.25 dB
VCO tuning range 3.36GHz ~ 3.87GHz
VCO 3.64 mW
I/Q divider 5.56 mW LO generator 6.97 mW
Mixer 9.05 mW
Adder 14.89 mW
Power Consumptions
Overall 40.11 mW
Chapter 3
Front-End Receiver with I/Q Mismatch Calibration
The function of our direct-conversion receiver is introduced in Chapter 1. In addition to the quadrature LO generator, the receiver requires the programmable front-end, including a variable-gain type LNA and a pair of gain-switch down-conversion mixer. Fig 3.1 gives an overall view of receiver block diagram. The quadrature LO generator is implemented by that mentioned in chapter 2. The LNA and mixer design will be introduced in the following.
Fig. 3.1 Receiver block diagram
3.1
Front-End Link Budget
The IEEE 802.11a standard specifies over a generous 300-MHz allocation of spectrum for unlicensed operation in the 5-GHz block. Of that 300-MHz allowance, there is a contiguous 200-MHz portion extending from 5.15 to 5.35 GHz, and a separate 100-MHz segment from 5.725 to 5.825 GHz, whereas the output power cannot exceed 40 mW for channels from 5.15 to 5.25 GHz or 200 mW for channels from 5.25 to 5.35 GHz. Fig 3.2 shows a lower frequency band of the channel allocation [1]. To determine the precise target value, the specification sets frequency range, noise figure, maximum input signal level (input-referred 1-dB compression point). For frequency range, it is often acceptable to cover only the lower 200-MHz band. The upper 100-MHz domain is not contiguous with that allocation, so its coverage would complicate somewhat the design of the synthesizer. Furthermore, that upper 100-MHZ spectrum is not universally available, such as HIPERLAN. Hence,
Fig. 3.2 IEEE 802.11a lower frequency band of the channel allocation
the receiver at the frequency band of 5.15-5.35GHz is our design goal. The specification simply recommends a noise figure of 10dB, with a 5-dB implementation margin. In order to accommodate the worst-case situation and gain more margins, maximum noise figure of 7dB is the design target for this receiver. The standard also specifies a value of –30 dBm as maximum input signal that a receiver must accommodate (for a 10% packet error rate). Converting this specification into a precise IIP3 target or 1-dB compression requirement is nontrivial. However, as a conservative rule of thumb, the 1-dB compression point of receiver should be about 4 dB above the maximum input signal power level that must be tolerated successfully.
Based on this approximation, the target of input-referred 1-dB compression point has to be better than –26 dBm [11]. Furthermore, the IIP3 is about 9.6dB higher than the 1-dB compression point; therefore, the target of IIP3 is set to -16dBm.
According to the Friis equation, we can calculate the effect of each stage in a cascade upon the signal, noise, and IIP3. For the noise figure of cascaded stages, the total NF can be written as equation (3.1). For the linearity of a general expression for cascaded stages, the overall IIP3 can be equation (3.2). Table 3.1 lists the receiver front-end link budget under different gain modes and shows the overall performances.
1
Table 3.1 Estimated front-end link budget (High gain mode / Low gain mode)
LNA Mixer Overall
Conversion Gain 22 / 8 12 / 6 34 / 14
Noise Figure 2 / 6 14 / 15 6 / 12
IIP3 -12 / -4 6 / 12 -24 / -10
3.2
Low Noise Amplifier Design
In RF system, the LNA, one of front-end circuits, locates on the receiving path of transceiver. The main functions are amplifying RF signal received from the antenna, providing input impedance matching and contributing as minimal noise as possible for the system working well.
3.2.1 Principle of the circuit design
Low Noise Amplifier, which constitutes the front-end of RF receivers, should have enough power gain to suppress the noise characteristic for the latter stages.
However, when the signals with about -30dBm, the maximum input power of the IEEE 802.11a specification, are amplified by such high gain LNA, the output of the LNA exceeds the input dynamic range of the following stages. This would then result in undesired distortion of the mixer output, i.e. intermodulation. Therefore, in order to achieve high sensitivity and high linearity, the LNA should have a variable gain control function. At the time of a weak signal input, the LNA is set at a high gain mode to achieve the required high sensitivity, while at the time of a strong signal input
However, when the signals with about -30dBm, the maximum input power of the IEEE 802.11a specification, are amplified by such high gain LNA, the output of the LNA exceeds the input dynamic range of the following stages. This would then result in undesired distortion of the mixer output, i.e. intermodulation. Therefore, in order to achieve high sensitivity and high linearity, the LNA should have a variable gain control function. At the time of a weak signal input, the LNA is set at a high gain mode to achieve the required high sensitivity, while at the time of a strong signal input