Chapter 4 Low Spur Frequency Synthesizer
4.4 Simulation Results
Fig. 4.14 Schematic of the unity gain buffer used in the charge pump
4.4
Simulation Results
Fig 4.15 shows that output frequency of VCO versus control voltage with switching band and reveals that 3.32GHz ~ 3.69GHz is covered. Fig 4.16 and Fig 4.17 show that prescalar output waveforms at different modules. Fig 4.18 shows that Current pump current matching condition and reveals that current mismatch is less than 3% between 0.4V and 1.4V of control voltage. Fig 4.19 shows that replica switching pair avoids charge sharing effect. Fig 4.20 shows that PFD dead zone simulation and reveals the operating is very linear and zero dead zone. Fig 4.21 shows that close-loop response simulation and reveals that lock time is about 18us. Table 4.3 lists the synthesizer performance summary.
Fig. 4.15 Output frequency versus control voltage with switching band
Fig. 4.16 Output waveform of dividing by 8
Fig. 4.17 Output waveform of dividing by 9
Fig. 4.18 Current pump current matching condition
Fig. 4.19 Replica switching pair avoids charge sharing effect
Fig. 4.20 PFD dead zone simulation
Fig. 4.21 Close-loop response simulation
Table 4.3 Synthesizer performance summary
-117 dBc/Hz( < -113 dBc/Hz )
TSMC 0.18-"""" m / 1.8V Process / Supply
TSMC 0.18-"""" m / 1.8V Process / Supply
Chapter 5 Conclusions
In chapter 2, the proposed I/Q mismatch calibration techniques has been implemented using TSMC 0.18um CMOS technology. Frequency plan of the LO generation avoids VOO-pulling and reduce LO-RF interaction. And calibration performance is evaluated by measuring the image-rejection ratio (IRR). The measured IRR after calibration is 28.25dB. According to measured IRR, we estimated that gain error is about 0.66dB and phase error is less than 1.
In chapter 3, a 1.8V, 5-GHz direct conversion front-end receiver using TSMC 0.18um CMOS technology is proposed. By calibrated techniques mentioned in chapter 2, measured results show that I/Q phase error less than 0.6 and gain error less than 0.2dB can be achieved, thus I/Q phase and gain calibrations were implemented successfully. In addition, adaptive gain control of both LNA and mixer provides the feasibility for optimizing its gain, noise, and linearity performance. This I/Q calibration technique facilitates the realization of high performance and high yield RF receiver in a generic CMOS process. It consumes chip area of 1.64mm2 and power of 37.25mW at 1.8V supply voltage.
In chapter 4, a frequency synthesizer operating at 2/3 of required RF frequency has been implemented. A novel charge pump with improved current matching is
proposed to effectively reduce reference spurs. And low phase noise frequency synthesizer design methodology is proposed. It consumes chip area of 1.06mm2 and power of 14.4mW at 1.8V supply voltage.
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