In Chapter 2, an overview of the previous Burst-Mode CDR related works are introduced. In the beginning of this chapter, the traditional Burst-Mode CDR architectures are presented. The details of the design issues and challenges of the previous researches are included in the end of this chapter.
Chapter 3 introduces the operational principal of the CDR circuit which realizes jitter reduction and its design concepts. In the end of the chapter, the circuit block used in this architecture and the whole system’s simulation results will also be described.
Chapter 4 first presents the chip information, the settings for measurement including the measurement instruments for the Burst-mode CDR and then the measurement results of the chip will be discussed at the end of this chapter.
In Chapter 5, the conclusion of our research is given and the future work is also presented.
Chapter 2
Introduction of the GVCO-Based Burst-Mode Clock and Data Recovery Circuit
At the begin of this chapter, the literature review of burst-mode CDR is introduced from which we can be familiar with the operation principal of burst-mode CDR. At the end of this chapter; we will find the details of the issues and the design challenges of previous CDR works.
2.1 Literature Review
2.1.1 Phase-Lock-Loop
A conventional PLL [13] [3] is composed of a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a divider. The typical PLL model is shown in Fig. 2.1:
Figure 2.1 PLL model [13]
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
2.1.2 Burst-Mode Clock and Data Recovery Circuit
GVCO-based CDR can be seen in many fast locking applications such as GPON.
The architecture of traditional one is proposed in ref. [10], [11] and is shown in Fig.
2.2.
Figure 2.2 Traditional structure of BMCDR Circuit [10][11]
The structure adopts three GVCOs which all operate at the same frequency which is input data rate. Through this structure, although it is very fast locking, however, the three GVCOs must be adopted while run at full rate which consume power very well, as a result, under power consumption consideration, the architecture is phased out.
A better architecture using an edge detector in ref. [1], [2], [8], [12] is adopted lately, which is shown in Fig.2.3. We can observe that only one GVCO in the CDR core is used, moreover, both the GVCOs can even work at half of input data rate [2],
CDR core
[8]. In other words, through only one half-rate GVCO used in the CDR core, both power and area can be saved. Unfortunately, a requirement of precise half of bit time (Tbit/2) delay in the edge detector is required in such architecture or degrades the jitter performance [12].
Figure 2.3 Half-Rate Burst-Mode CDR using the edge detector [1], [2], [8], [12]
CDR core
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
2.2 Design Challenges of Burst-Mode CDR
From previous discussion, we can understand the basics and the operation principal of the Burst-Mode CDR. To be used for several gigabits input data rate of GPON system, there are some design issue in the CDR system, which are:
Locking Time
For GPON applications, the locking bit of the CDR within less than 10 bits is required. Conventional close-loop-based CDR may not be used for these applications. Therefore, open-loop-based CDR architecture is often adopted here.
Jitter
Imprecise value of half of bit time (Tbit/2) delay in the edge detector of open loop path degrades jitter performance [12]. In practice, however, it is impossible to control the delay time to a value to Tbit/2 exactly due to process and environmental variation. Therefore, there must be a well controlled mechanism to minimize such jitter generation in the edge detector.
Power
For a CDR with several gigabits per second input data rate, the two GVCOs used in both open loop and close loop path are often required. As a result, large power consumption is inevitable.
2.3 Jitter Issue in Conventional Burst-Mode CDR
The block diagram of a conventional Burst-Mode CDR which adopts an edge detector is shown in Fig. 2.4. To have the best jitter performance of the CDR circuit, the delay in the edge detector must be set to optimum value of half of bit time (Tbit/2) [12]. However, jitter generation in the open loop path of BMCDR circuits cannot be suppressed effectively by traditional approaches. Generally speaking, the more precise value of half of bit time (Tbit/2) delay in the edge detector is, the better is the jitter performance.
Figure 2.4 Block diagram of conventional Burst Mode CDR [1], [2], [8], [12]
Let us examine the amount of recovered clock jitter through the simulation results when imprecise value of half of bit time (T /2) delay in the edge detector
CDR core
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
exists. In Fig. 2.5, we can observe that the amount of recovered clock jitter is dominated by two factors; one is the run length of input data while the other one is the degree of imprecise value of Tbit/2.
Figure 2.5 Recovered clock Jitter versus degree of imprecise value of Tbit/2 and run length of input data.
As a result, there should be a well-controlled tuning mechanism of half of bit time (Tbit/2) delay in the edge detector. Unfortunately, in practice, with temperature and process variation, it is impossible to control the delay time in edge detector to an optimum value exactly equals Tbit/2. Recently published Burst-Mode CDR papers in ref. [1], [2], [6] try to use on chip inverter chain or an external chip [12] to realize half-bit time (Tbit/2) delay. However, due to variation of process, these methods may still result in jitter generation, which also forms jitter in recovered clock. Thus, to ensure minimum jitter generation, an interesting way to produce half of bit time (Tbit/2) delay precisely in the edge detector is presented in Chapter 3.
Degree of imprecise value of Tbit/2
Chapter3
A 1.25 GB/s Burst-Mode Clock and Data
Recovery Circuit with Jitter Reduction Technique
_____________________________________________________________________
This chapter starts from the introduction of the system architecture of Burst-Mode CDR with jitter reduction feature. After going through the introduction of system operation principal, we will see the details of every building block used in this design. Finally, the whole system simulation results are interpreted.
3.1 System Architecture
Half rate architecture of the burst-mode CDR circuit developed in ref. [8] is adopted in this work to realize jitter reduction, as shown in Fig. 3.1. The operation principal is similar to the traditional half-rate one with edge detector which is introduced in chapter 2. This architecture not only saves chip area but also consumes less power.
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
3.2 Methodology for Jitter Reduction
The edge detector adopted here is developed in ref. [8] and is used to combine with the proposed half of bit time (Tbit/2) delay generating circuit to produce accurate half of bit time (Tbit/2) delay in the edge detector. The edge detector circuit is illustrated in Fig.3.2. The half of bit time (Tbit/2) delay generating circuit, as shown in Fig. 3.3, is adopted in the edge detector.
To produce half of bit time (Tbit/2) delay in the edge detector, recently published Burst-Mode CDR papers use on chip inverter chain to realize in ref. [1], [2], [6] or utilize an external chip to switch between just two delays to generate half of bit time (Tbit/2) delay in ref. [12]. However, these methods that produce the delay [1], [2], [6]
or the average delay [12] is still not necessarily falls exactly on Tbit/2 due to process variation. It will results in jitter generation, too. In this work, differing from ref. [12], a concept that many delays (more than 2) can be chosen and then being “weighted average” to produce half of bit time (Tbit/2) delay is proposed, that is, through switching between them with unequal weighting factor producing a delay that equals exactly to half of bit time (Tbit/2) delay. The purpose is to further reduce jitter in the time domain by suppressing harmonic tone in the frequency domain resulting from switching between only two delays periodically. In the design, four delays that are nearest to optimum delay of Tbit/2 result in minimum recovered clock jitter are chosen and then to be alternatively switched between each other and through weighted average to create a delay that fall exactly on Tbit/2. By post layout simulation, the recovered clock jitter has better jitter performance when switching between four delays than switching between only two delays that also result in exactly Tbit/2 through “weighted average” method. Table 3.1 shows the delay and its relative
recovered clock jitter. Table 3.2 shows the delays produced by switching between delays that are nearest to Tbit/2 through “weighted average” method and their relative recovered clock jitter.
Figure 3.2 (a) The rising edge detector [8] with proposed Tbit /2 delay generating circuit and (b) falling edge detector [8] with Tbit /2 delay generating circuit
Figure 3.3 Tbit /2 delay generating circuit.
Table 3.1 The delay and their relative recovered clock jitter
delay 4 5 6 7 8
Clock Jitter (ps) 118 105 120 139 152
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
Table 3.2 The delay and their relative recovered clock jitter.
delay 5.125 5.25 5.3125 5.375 5.5 5.75 recovered clock Jitter (switching
between two delays) (ps)
99 96 88 92 98 113
recovered clock Jitter (switching between four delays) (ps)
82
3.3 Circuit Description
In this section, each circuit block composing the whole burst-mode clock and data recovery circuit is introduced and the simulation results of each block and the whole system simulation results are addressed, too.
3.3.1 Phase-Lock-Loop
The PLL is composed of a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a divider. The PLL with second-order loop filter is chosen in this design as shown in Fig. 3.4.
Figure 3.4 Architecture of the PLL
The phase frequency detector of the PLL adopted here is proposed in ref. [14] is shown in Fig. 3.5. The simulation results of the PFD with charge pump is illustrated in Fig.3.6 and the simulation result of charge pump current mismatch is shown in Fig.
3.7. The divide-by-5 divider developed in ref. [15] is used here and the simulation result is shown in Fig. 3.8.
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
(a)
(b)
Figure 3.5 (a) PFD schematic [14] and (b) the function
Figure 3.6 Characteristic plot of the PFD-CP
(b)
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
(a)
(b)
Figure 3.8 (a) Schematic [15] and (b) simulation result of the divide-by-5 divider
The phase margin of this PLL is designed larger enough for the system stability consideration in this design. While the ring VCO adopted here is developed in ref. [20]
which consists of two delay cells for power saving and the delay cell is shown in Fig.
3.9.
Figure 3.9 Circuit implementation of the delay cell of the ring oscillator. [20]
To reduce the VCO gain, a bias circuit introduced in ref. [22] is shown in Fig.
3.10. It is adopted here to reduce the VCO gain. The simulation result of the overall tuning curve of the VCO under FF, TT, SS corner is shown in Fig. 3.11.
Figure 3.10 Schematic of bias circuit for VCO. [22]
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
Figure 3.11 Simulation result of the two stage ring VCO with the bias circuit.
3.3.2 Clock Recovery Circuit (CRC)
The CRC adopted here is proposed in [8], which is with the features of low power consumption and instantaneous clock recovering. Fig. 3.12 shows the schematic of the CRC while Fig. 3.13 shows the simulation result of the CRC.
Figure 3.12 Circuit implementation of the CRC [8]
Input Data
Recovered Clock
Recovered Data1
Recovered
Data2
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
3.3.3 Decision Circuit
The decision circuit is composed of current-mode logic circuit due to its high speed advantages while large power consumption is inevitable. The current-mode DFF developed in ref. [21] is used here, as shown in Fig. 3.14.
Figure 3.14 Decision Circuit [21]
3. 4 Whole System Simulation Results
Through the matlab simulink behavior model of PLL, the transient response of the PLL is simulated. Fig. 3.15 and Fig. 3.16 illustrate the behavior level transient response and frequency response of the PLL. Fig. 3.17 shows the post layout simulation of transistor level transient response of PLL.
Figure 3.15 Behavior level transient response of PLL.
Figure 3.16 Behavior level frequency response of PLL
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
Figure 3.17 Transistor level transient response simulation result of PLL.
After PLL is locked, a test pattern of 1.25-Gb/s PRBS is sent to the CDR. The waveforms are shown in Fig. 3.18, including input data, the control voltage on the PLL, recovered clock, and two recovered data sequences.
Vctrl
Input Data
Recovered
Clock
Recovered
Data2
Recovered
Data1
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
Figure 3.18 Recovered clock and recovered data from the CDR circuit
Fig. 3.19(a) shows the jitter histogram of the recovered clock, and Fig. 3.19(b) illustrates eye diagram of the retimed data. The recovered data eye diagram shows the Burst-Mode CDR with jitter reduction features meet the jitter mask of GPON specification. The total power consumption of the CDR is 32.1mW. Finally, table 3.3 gives the performance summary of the burst-mode CDR.
Recovered Data1
Recovered Data2
Recovered Clock
Input
Data
Vctrl
(a)
A 1.25 GB/s Burst-Mode Clock and Data Recovery Circuit with Jitter Reduction Technique
(b)
Figure 3.19(a) the jitter histogram of the recovered clock, and (b) the jitter histograms of the retimed data.
Table 3.3 Performance summary.
Pre‐SIM Post‐SIM
Technology 0.18µm CMOS 0.18µm CMOS
Input data
Rate 1.25Gb/s 1.25Gb/s
Supply Voltage 1.8v 1.8v Locking time 1 bit(0.8ns) 1 bit(0.8ns)
Power 31.93mW 32.1mW
Experimental Result
Chapter 4
Experimental Result
This chapter starts from the introduction of the chip information and then the measurement environment is presented. In the end of this chapter, the experimental results will be interpreted.
4.1 Chip Information
The burst-mode clock and data recovery circuit with an on-chip jitter reduction circuit is fabricated through National Chip Implementation Center in TSMC CMOS 0.18-μm technology. Fig. 4.1(a) shows the layout and Fig. 4.1(b) illustrates the die photo. The area is 0.99×0.97 mm2.
(a)
(b)
Fig.4.1 (a) The chip layout view (b) The chip photo view
Experimental Result
4.2 Measurement Consideration
4.2.1 Printed Circuit Board
Fig. 4.2 shows the photograph of the chip with the PCB. The chip is measured under 1.8v power supply.
Fig.4.2 The top view of PCB.
4.2.2 Measurement Environment Setup
Fig. 4.3 shows the setup for measurement. It is worth to mention that each digital control signal is generated by Acute PG 2050 controlled by a PC.
Figure 4.3 Measurement environment
Experimental Result
4.3 Experimental Result
When data stream is sent to the chip, we first measure the recovered clock jitter of the delays that are nearest to Tbit/2. From the simulation results, we know that the more precise value of half of bit time (Tbit/2) delay in the edge detector is; the better is the jitter performance. Base on the result, we found 4 delays in the delay line that have less recovered clock jitter, which are delay 4, delay 5, delay 6, and delay 7, the corresponding recovered clock jitter are 160ps, 150ps, 130ps, 175ps, respectively, as Table 4.1 shows. If we choose the delay that is too far away from Tbit/2, in this case, delay 11, the recovered clock jitter would be extremely large as shown in Fig. 4.4.
Table 4.1 The delay and corresponding recovered clock jitter
delay 4 5 6 7 11
P-P Jitter(ps) 160 150 130 175 310
Figure 4.4 Measurement results of recovered clock jitter based on different delay time.
Second, we try to find the probably location of Tbit/2. Due to have less recovered clock jitter of delay 5 and 6, we can judge that Tbit/2 must fall between the two delays, and then, a stream of random pattern that generates delay of 5.5 is sent to the chip; the measured recovered clock jitter (peak-peak) is 123.5ps at 540MHz, as shown in Fig.4.5. After that, two random patterns that generates delay of 5.333 and 5.667 are sent to the chip, the measured recovered clock jitter (peak-peak) are 124.0ps at 540MHz and 121.2ps at 540MHz, respectively, which are shown in Fig. 4.6 and Fig.
4.7. We can observe that the Tbit/2 may fall between delay 5.667 and 6, and then, two random patterns that generates delay of 5.7 and 5.78 are sent to the chip, the measured recovered clock jitter (peak-peak) are 116.5ps at 540MHz and 114.3ps at 540MHz, respectively, which are shown in Fig. 4.9 and Fig. 4.10. Table 4.2 illustrates the relationship between delay and recovered clock jitter. Generally speaking, the more precise value of half of bit time (Tbit/2) delay is, the better is the jitter performance.
Experimental Result
Figure 4.5 When delay is 5.5, the recovered clock jitter (peak-peak) is 123.5ps at 540MHz
Figure 4.6 When delay is 5.33, the recovered clock jitter (peak-peak) is 124.0ps at 540MHz
Figure 4.7 When delay is 5.66, the recovered clock jitter (peak-peak) is 121.2ps at 540MHz
Figure 4.8 When delay is 5.68, the recovered clock jitter (peak-peak) is 118.8ps at 540MHz
Figure 4.9 When delay is 5.7, the recovered clock jitter (peak-peak) is 116.5ps at 540MHz
Figure 4.10 When delay is 5.78, the recovered clock jitter (peak-peak) is 114.3ps at
Experimental Result
Table 4.2 The relationship between delay and recovered clock jitter
Clock Jitter v.s. Average Delay Value
0 100 200
5 5.33 5.5 5.66 5.68 5.7 5.78 6 Average Delay Value
R eco ve re d C lo ck Ji tte r
Clock Jitter v.s.
Average Delay Value
4.4 Experimental Results Summary
The measurement results of recovered clock jitter show the more precise value of Tbit/2 is, the better is the jitter performance. When probably position of Tbit/2 is found, a calibration pattern can be fed into Tbit/2 delay generating circuit to calibrate recovered clock jitter. The recovered data is not available due to my careless layout about current density (2.5mA/0.22μm) which results in burning in metal line of output DFF. Fig. 4.11 shows the die photo of the decision circuit, which illustrates the metal line was burned, thus, the DFF cannot work properly. Table 4.3 shows the comparison between pre-layout simulation, post-layout simulation, and measurement results of the Burst-Mode CDR circuit. The results all illustrate significant jitter reducing when jitter reduction technique is enable.
Figure.4.11 Burning out of metal line of the decision circuit.
Experimental Result
Table 4.3 Burst-Mode CDR performance summary
Pre‐SIM Post‐SIM(1) Post‐SIM(2) Measurement
Technology 0.18µm CMOS 0.18µm CMOS 0.18µm CMOS 0.18µm CMOS
Input data
Rate 1.25Gb/s 1.25Gb/s 1.08Gb/s 1.08Gb/s
Supply
Voltage 1.8v 1.8v 1.8v 1.8V Locking time 1 bit(0.8ns) 1 bit(0.8ns) 1 bit(0.8ns) N/A
Power 31.93mW 32.1mW 30.6mW 36mW
4.5 Performance Comparison
Table 4.4 shows the comparison of the burst-mode clock and data recovery circuit.
Table 4.4 Burst-Mode Clock and Data Recovery performance comparison
[6] [5] [12] This Work
Conclusion and Future Works
Chapter 5
Conclusion and Future Works
5.1 Conclusion
In this thesis, a Burst-Mode CDR with jitter reduction technique is presented. The design challenges of this design is discussed and solved. This work integrates a Tbit /2 delay generating circuit into the burst-mode CDR chip to realize jitter reduction.
The measurement results show that the more precise value of half of bit time (Tbit/2) delay in the edge detector, the better is jitter performance. When jitter reduction technique is disabling, the measured recovered clock jitter is 130ps, while the jitter reduction technique is enable, the measured recovered clock jitter is 114.3ps, reduced by 13.7%. When probably position of Tbit/2 is found, a calibration pattern can be fed into Tbit /2 delay generating circuit to calibrate recovered clock jitter. The chip size is 0.99 0.97 mm². The power consumption of the CDR is 36mW under 1.8V power supply. The designed Burst-Mode CDR is fabricated in TSMC 0.18 μm 1P6M CMOS process.
5.2 Future Works
This work introduces the idea that the more precise value of half of bit time (Tbit/2) delay in the edge detector is, the better is the jitter performance. From the experimental results, a feedback circuit used for detecting the location of Tbit/2 position can be added in the future work to produce calibration pattern automatically, and then calibrate the recover clock jitter.
Recently published Burst-Mode CDR related papers operates up to 10 gigabit/s.
Therefore, higher operation frequency of Burst-Mode CDR must be developed. The calibration scheme of the jitter reduction circuit would also be useful by replacing the static logic circuits in Tbit /2 delay generating circuit with current mode logic circuits for better resolution.
Finally, the divider of the Burst-Mode CDR can be further improved to satisfy all the input data rate operation of GPON specification.
Bibliography
Bibliography
[1] M. Nogawa, K.Nishimura, S. Kimura,Yoshida, T.Kawamura, M.Togashi, K.
Kumozaki, and Y.Ohtomo, “A 10Gb/s burst-mode CDR IC in 0.13um CMOS,”
IEEE International Solid-State Circuits Conference, pp.228-229, Feb. 2005.
[2] Yu-Gun Kim, Chun-Oh Lee, Seung-Woo Lee, Hyun-Su Chai, Hyun-Suk Ryu, Woo-Young Choi, “Novel 622Mb/s Burst-Mode Clock and Data Recovery
[2] Yu-Gun Kim, Chun-Oh Lee, Seung-Woo Lee, Hyun-Su Chai, Hyun-Suk Ryu, Woo-Young Choi, “Novel 622Mb/s Burst-Mode Clock and Data Recovery