Chapter 1 Introduction
1.2 Organization
This thesis was constructed from six chapters. It was devoted to the design of an UWB CMOS LNA and a new broadband switch using InGaAs pHEMT.
Chapter 1 introduces the motivation of the research and the arrangement of this thesis.
In chapter 2, the topologies in common use of LNA will be introduced. Each of them has different advantages with different design architectures. We will make a description for the four kinds of different topologies and choose the most suitable one for wideband applications. In addition, the survey of recent low-noise amplifiers will also be listed in this chapter.
In chapter 3, a LNA whose bandwidth ranges from 2.6 GHz to 8.6 GHz will be presented. The architecture uses 1
gm termination topology as the first stage. To
achieve wideband performance, we introduce some gain matching components at the third stage. The simulated results will be listed in the end.
In chapter 4, the design methodology of broadband switches and various switching devices will be introduced, and switch configurations will also be presented.
In chapter 5, the design theory and the design flow of a SPDT switch will be introduced here. The bandwidth of the switch is ranged from 33 GHz to 60 GHz. The simulated and measured results will be listed in the last.
In the last chapter, we will make the summary and indicate some suggestions for the future design.
Chapter 2
Design Methodology of Low Noise Amplifier
2.1 Overview
This chapter is composed of three sections; first, simple description of CMOS foundry will be listed. Second, noise sources and four basic topologies of low noise amplifiers will be discussed in detail. Finally, we will discuss the state of the art for UWB LNAs.
2.2 Noise Sources
The output noises are mainly come from thermal noises. Besides the thermal noise of resistances (in R, ), there are the thermal noise of the channel current (in d, ) and induced current noise factor.
2.3 The basic topologies of LNAs
For the LNA circuits, a resistive impedance matching between the LNA and the driving source is a critical requirement. It is difficult to provide good impedance
matching to the source without degrading the noise performance because the input of the LNA circuits is connected to a capacitive node. There are various matching methods that have been applied to improve LNA performance. On the basis of these matching methods, the LNA topology can be sorted by four kinds [3]:
Resistive Termination The 50Ω resistance is connected to the input node of a
common source amplifier directly and the architecture is shown as Fig. 2.1(a). The connection means that the input source can see only the resistor over reasonable broadband. Nevertheless, the resistance which is connected directly to the input terminal weakens the signal ahead of the transistor and brings thermal noise of its own.
This topology is rarely used in the LNA design because of its unacceptable high noise figure.
1/g Termination The input impedance is set by the 1/m g of the transistor in m the common gate stage shown as Fig 2.1(b). This architecture is very simple and can easily achieve the appropriate impedance matching. This topology seems to be a good choice for a wide bandwidth system because the transistor’s g is merely affected m in the frequency range of UWB system. In order to make 1/g =50Ω, the value of m g has to be fixed at 20mS. This means that the transistor size has to be fixed and m
this will affect the noise figure of the single transistor system. The gain of this LNA is also fixed without increasing output resistance. Therefore, there will be more than one stage when using this type topology to enhance the overall gain.
In the common gate configuration, the noise figure and the matching circuits totally depend on the single transistor in the common gate stage. The equation 2.1 shows the noise figure of the single transistor [3].
α +γ
= 1
F (2.1)
where γ is the coefficient of channel thermal noise and α is
0 the long channel device, γ equals to 2/3 and α equals to 1. For the short channel case, the value of γ is greater than 2/3. Based on these data, the best noise figure of this 1/g termination topology tends to be more than 2.2dB. Consequently, this topology m can afford quite wide bandwidth impedance matching but bring a large noise figure and is difficult to achieve high gain performance.
Shunt-Series Feedback The architecture is shown as Fig. 2.1(c). With the shunt
series feedback architecture, the bias point of the input is fastened with the output voltage. For this reason, the biasing point of this system is not set to the optimal bias point. This will cause an extra power consumption to achieve the desired gain.
Moreover, the shunt series feedback architecture has a stability problem.
Usually the shunt series feedback can be analyzed as equation 2.3.
⎥⎥
. From the S-parameter matrix, the ideal matching condition is S11 = S22 =0, the series resistance R can be calculated as S
m f
S R g
R = Z02 − 1 . (2.4)
Substituting 2.4 in to 2.3 attains S-parameter
⎥⎥
R , we can achieve the goal of very wide bandwidth and flat gain. The only S
restriction of this architecture is that the source resistance R must be nonnegative. S If R becomes negative the system will oscillate. This limitation puts bounds to the S value g of the transistor with desired gain m S . 21 Therefore a transistor satisfying the condition of equation 2.6 can be selected in the negative feedback configuration. This analysis is only valid for low frequencies where all reactance components can be neglected. In the case of UWB systems, the parasitic capacitance and inductance can not be neglected. Because of the undesired effects of parasitic, not only the gain degradation but also the noise figure raising will happen at high frequency. Besides, the stability drops to the unstable region because of the feedback effect. This type of configuration must improve its gain and noise figure at high frequency without reducing stability.
With this configuration, it requires very high power consumption to increase the gain because the bias point of the system is fixed at the output voltage, which is not the optimal DC biasing point. However, the architecture gives wide bandwidth characteristic for the UWB system.
Inductive Degeneration The last topology is displayed in the figure 2.2(a).
From the small signal model shown as Fig. 2.2(b), the input impedance of this architecture can be calculated as
S At the resonant frequency, the input impedance is purely real and proportional to L . S Therefore, this system don’t have to add additional any resistive components and it can reach the input impedance matching by choosing appropriate value of the L . S This leads to a very good noise figure and impedance matching for a narrow
bandwidth system. However, since this topology utilizes resonance at the desired frequency, it can be used only for narrow bandwidth signals and it is not suitable for wide bandwidth applications.
2.4 State-of-the-art LNAs for UWB application
Recently, there are several low-noise amplifiers designed for UWB systems. The general architectures can be sorted for three kinds; one is choosing an inductive degeneration topology which a broadband filter is located in front of. The second is selecting a common gate topology as the first stage in addition to more stages to enhance the power gain and the bandwidth and the third is using a shunt-series feedback configuration. Even though the first kind makes use of inductive degeneration which can afford lowest noise figure, this architecture also utilizes many passive components which will introduce higher noise figure. The second kind utilizes common gate architecture to achieve input matching, but it usually has more than 1 stage and leads to more power consumption. Low noise figure and power consumption are two important features in UWB system. The third kind uses feedback to enhance the bandwidth but this will lead to the problem of stability. In order not to lead the circuit to unstable, the value of resistor must be chosen carefully.
The disadvantage of the feedback topology is that the circuit is very sensitive to the process variation of the foundry. If the circuit was designed near the boundary of the stable circle, the circuit will introduce oscillation even with little process errors. It seems that there is no perfect design of low-noise amplifiers for UWB systems so far.
2.4.1 Broadband filter with source inductive degeneration LNA
In September 2001, Pietro Andreani and Henrik Sjoland published a method to optimize noise of inductively degenerated CMOS low-noise amplifier [4]. The
simplified schematic is shown in Fig. 2.3. They mainly discussed the relationship between Q, channel noise and gate induced current noise. When the value of Q is increasing, the channel noise decreases but it also leads the gate induced current noise to increase. The capacitor C has the function of decoupling Q from d C , which gs
allows for an adjustable reduction of Q for any given value of C . This architecture gs is only suitable for narrow band application. In 2004, this circuit was improved for wide-band use. Andrea Bevilacqua and Ali M Niknejad added two inductors (L L1, 2) and capacitors (C C1, 2) in front of the previous circuit as shown in Fig. 2.4. These passive components form a three-section band-pass filter to resonate its reactive part over the whole band. In this way, it can achieve the wideband input impedance matching. Its 3 dB bandwidth ranges form 2.4 to 9.5 GHz and power consumption is 9 mW [5].
2.4.2 Low noise amplifier with active input matching
This architecture utilizes the characteristic of common-gate topology to achieve the input impedance matching. A circuit presented in 2004 is shown as Fig. 2.5. The resistance looking into the source terminal is 1 g and proper choice of bias current m can get the desired 50Ω. The second stage uses a feedback topology to enhance the bandwidth and increase total gain. The addition of L makes more gain and it do not f lead the circuit to oscillate. At some frequencies, the phase of output voltage is in-phase with input voltage (positive feedback). L can also avoid this situation to f
happen. The capacitance C blocks the DC current that comes from the output node. f The bandwidth of this circuit ranges from 3.1 to 6.1 GHz and its gain is around 17 to 15.5 dB [6].
2.4.3 Low noise amplifier with feedback
A shunt-series feedback topology LNA schematic is shown in Fig. 2.6. In the figure, the load inductance L2 substitutes for the resistive load of the original configuration. The impedance of the inductor increases as the frequency increases and this can compensate for the amplifier degradation at high frequency. The inductor L1 is added for additional gain boost at high frequency. The C is used for DC blocking. f This capacitance blocks the DC current that comes from the output node. The transduced gain is 8.5 dB and has a variation of ± 0.2 dB. The noise figure is 3 dB [7].
We make a table to compare some wide-band LNAs shown in Table 4.1. Input 1dB compression point and IP3 are merely concerned in case of UWB LNA because in general the transmit power is limited to be less than -42dBm/Hz.
(a) (b)
(c)
Fig. 2.1 LNA topologies: (a) Resistive Termination, (b) 1 g Termination, (c) m Shunt-series Feedback
(a) (b) Fig. 2.2 Inductive degeneration : (a) topology, (b) small signal model
Fig. 2.3 Simplified schematic of a low noise amplifier with inductive source degeneration.
Fig. 2.4 Simplified schematic of wideband low noise amplifier
Fig. 2.5 Circuit schematic of wideband LNA with active input matching
Fig. 2.6 Circuit schematic of wideband LNA with feedback
[5]
measured
[6]
Simulated
[7]
Simulated
This work Simulated Technology 0.18 um CMOS 0.18 um CMOS SiGe 0.5 um 0.18 um CMOS Band (GHz) 2.4 to 9.5 3.1 to 6.1 0.8 to 1.6 2.6 to 8.6
Bandwidth 7.1 (3dB) 3 0.8 6
S11 (dB) <-9.4 -12.9 to -18 N/A <-9.4
S21 (dB) 10.4 (max) 17 to 15.5 8.5 ± 0.2 17.6 to 15.6
S12 (dB) <-35 <-43 N/A <-44.5
NF (dB) 4.2 to 8 3.9 to 4.3 about 3 5.58 to 6.6
Power (mW) 9 21 23.1 24
Area(mm ) 2 1.1 1.86 x 1.36 N/A 1
Table 2.1 Comparison of wideband low noise amplifiers
Chapter 3
UWB CMOS Low Noise Amplifier
3.1 Overview
This chapter will present a 2.6-to-8.6 GHz low-noise amplifier using a 0.18 um CMOS process. It is based on the analysis in chapter 2. The foundry description, design and simulation of the circuit will be shown in the following.
3.2 CMOS foundry description
The CMOS device used in this design is fabricated by TSMC Semiconductor Corporation with a deep N-well 0.18-um process, and the Deep N-Well structure is shown as Fig. 3.1. This CMOS process provides academic users only as it is fabricated through TSMC provided shuttle. It possesses 1 poly layer and 6 metal layers with low k inter-metal dielectric. Deep N-well, MiM capacitor, high poly resistor, multi-Vt device and thick top metal are available for 1.8V/3.3V applications.
It is suitable for logic, mixed signal, and RF designs [8].
3.2 Circuit Design
In order to achieve the wide-band input impedance matching and flat gain, I utilize the multistage architecture. Using multistage architecture can expand the overall bandwidth [9]. There are 4 stages in this circuit totally, as shown in Fig. 3.2.
First stage is a common gate structure in order to achieve the impedance match of 50Ω. The input impedance is close to 1 g and m g is not much affected by m frequency of the bandwidth range, so it can achieve the wideband input matching. The
second common source structure is for gain boost. The third source inductive degeneration cascade architecture can not only enhance the gain but also reinforce the reverse isolation. Reverse isolation is a crucial factor because LNA is often put in front of mixer. In order to avoid the local oscillator leaking back to the LNA, it’s better to choose a LNA with good reverse isolation for systems. The final stage is just used as a buffer to permit the output impedance to be dropped to around 50Ω.
The first and final stages utilize two current sources to bias the circuit, so the current mirrors should be integrated into the circuit. The design of the current mirror is same as tradition except for the capacitor Cblock, as shown in Fig. 3.3. This capacitor can block the high frequency interference which is leaking from the drain node. If this capacitor was removed, the noise figure of the system will arise significantly.
Because we utilize common gate as the first stage, the thermal noise of channel current has a significant effect on system’s noise figure. In order to minimize the effect, we have an analysis for the relationship between ∆V, Ibias and in d2, where
Therefore, we can reduce the noise figure by decreasing ∆V and increasing Ibias. The drain bias voltage is 1.8 V and the gate bias voltage is 0.7 V. The bias voltage of current mirrors is adjustable in the range of 0 to 1.8 V. The layout of this low-noise amplifier is accomplished by the Cadence tools and is depicted in Fig. 3.4.
The chip size is 1 x 1 mm . 2
3.3 Simulation Results
The model used in this simulation is BSIM3v3 provided by the foundry. The performance of the low-noise amplifier is simulated with the commercial CAD software Advanced Designed System. The post-simulation are performed via a full-wave EM full-wave simulator SONNET.
The simulated gain and input, output return loss is depicted in Fig. 3.5. The reverse isolation is shown in Fig. 3.6. The minimum noise figure is 5.6 dB, as shown in Fig. 3.7. The total bandwidth is from 2.6 GHz to 8.6 GHz. The gain is 16dB ± 1 dB and input/output return loss are better than 10 dB. The reverse isolation is better than 44 dB. The stability factor K and Mu are also simulated, as shown in Fig. 3.8(a) and (b). The sufficient conditions for unconditional stable are K>1 and Mu>1 of two ports network.
The output power versus input power is simulated at 5.5 GHz, as shown in Fig.
3.9. The 1 dB compression point was -27 dBm at 5.5 GHz.
Fig. 3.1 The Deep N-well structure
Fig. 3.2 Simplified circuit of low noise amplifier
Fig. 3.3 Architecture of the current mirror
Fig. 3.4 Layout of LNA chip
Fig. 3.5 S11, S22 and gain from 1 GHz ~ 11 GHz
Fig. 3.6 Reverse isolation S12 from 1 GHz ~ 11 GHz
Fig. 3.7 Noise figure of LNA
(a) (b) Fig. 3.8 Stability Factor, (a) K>1, (b) Mu>1
Fig. 3.9 Output power versus input power
Fig. 3.10 The microphotograph of the UWB LNA
Chapter 4
Design Methodology of Broadband Switch
4.1 Overview
A switch can be applied to execute the multiple accesses, which is widely used and considered as a main choice in communication. It also reduces the duplicate of the circuits with the same functions. In low frequency range, the design of switches neglects the parasitic and transmission-line effects. On the contrary, these effects occur significantly in the millimeter-wave frequency range and must be taken into account in the switch design. This chapter has a full discussion on the design methodology of broadband switches.
4.2 Switching Devices
PIN diodes and FETs are two types of devices used commonly in the control circuits. Here, we discuss the significant properties of these devices.
PIN Diodes A PIN diode is a pn junction device that has a very minimally
doped or intrinsic region located between the p-type and n-type contact regions as illustrated in Fig. 4.1(a). The combination of the intrinsic or i-region results in characteristics that is very advantageous for certain device applications. In reverse bias the intrinsic region causes very high value for the diode breakdown voltage, whereas the device capacitance is reduced by the increased separation between the p- and n-region. In forward bias the conductivity of the intrinsic region is controlled by the injection of charge from the end regions. A practical PIN diode consists of a lightly doped p- or n-region between the highly doped p-type and n-type contact
region, as shown in Fig. 4.1(b) and Fig. 4.1(c). To identify very lightly doped p and n material, the Greek letters are used; consequently, lightly doped p material is called π-type and lightly doped n material is called ν-type. The diode is a resistor controlled by bias current with preferable linearity and low distortion. PIN diodes can provide faster switching speed and can handle medium to large RF power levels. They also make excellent RF switches, phase shifters and limiters. Sometimes the Schottky barrier diode (SBD) is applied for faster switching speed.
FETs In recent years PIN diode switches have been increasingly replaced by FETs based monolithic switches, especially for low to medium power applications.
The FET switches are three-terminal devices, in which the gate bias V controls the g states of the switch. The FET acts as a voltage controlled resistor, where the gate bias controls the drain-to source resistance in the channel. The intrinsic gate-to-source and gate-to-drain capacitances and device parasitics limit the performance of the FET switches at higher frequencies. In switching applications, a low-impedance (nearly short) state is obtained by making the gate voltage equal to zero. When the negative gate-source bias is larger than the pinch-off voltage in magnitude, the FET is in a high-impedance (nearly open) state. Fig. 4.2 shows the linear operation regions of a switching FET [10]. The configuration of a switching FET [11] is indicated as Fig. 4.3.
A low-impedance state can be adequately modeled by a resistance (R ) which is on series connection to a parasitic inductor (L ) between the source and the drain as on depicted in Fig. 4.4(a). A complete equivalent circuit in a high-impedance state is illustrated in Fig 4.4(b). The equivalent circuit is based on the device geometry from the reference [10], [12]. The off-state drain-to-source leakage resistance (R ) is ds generally large enough to be neglected in circuit modeling. The drain and the source are directly capacitive-coupled and through the gate (C ,ds C and gs C ). All of these gd
capacitances have series parasitic resistive elements (R and gs R for gd C and gs
C , gd R for d C ). A simplified FET model can be used without sacrificing accuracy ds
as shown in Fig. 4.5(a) and Fig. 4.5(b). The parasitic inductor was neglected for the on-state equivalent circuit. The off-state equivalent circuit has been reduced to a simple series resistor (Roff ) and a capacitor (Coff ). For the simplification, it is
as shown in Fig. 4.5(a) and Fig. 4.5(b). The parasitic inductor was neglected for the on-state equivalent circuit. The off-state equivalent circuit has been reduced to a simple series resistor (Roff ) and a capacitor (Coff ). For the simplification, it is