使用互補金屬氧化半導體製程之超寬頻低雜訊放大器及使用砷化銦鎵假型高速電子移動電晶體之寬頻開關

國 立 交 通 大 學

電信工程學系

碩 士 論 文

使用互補金屬氧化半導體製程之超寬頻低雜訊放大器

及使用砷化銦鎵假型高速電子移動電晶體之寬頻開關

UWB CMOS Low-Noise Amplifier

And

Wideband InGaAs pHEMT Switch

研 究 生：邱珮如 (Pei-Ju Chiu)

指導教授：鍾世忠 (Dr. Shyh-Jong Chung)

使用互補金屬氧化半導體製程之超寬頻低雜訊放大器

及使用砷化銦鎵假型高速電子移動電晶體之寬頻開關

UWB CMOS Low-Noise Amplifier

And

Wideband InGaAs pHEMT Switch

研 究 生：邱珮如 Student：Pei-Ju Chiu

指導教授：鍾世忠 博士 Advisor：Dr. Shyh-Jong Chung

國 立 交 通 大 學

電 信 工 程 學 系 碩 士 班

碩 士 論 文

A Thesis

Submitted to Institute of Communication Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master

in

Communication Engineering

June 2005

Hsinchu, Taiwan, Republic of China

使用互補金屬氧化半導體製程之超寬頻低雜訊放大器

及使用砷化銦鎵假型高速電子移動電晶體之寬頻開關

研究生：邱珮如 指導教授：鍾世忠博士

國立交通大學 電信工程學系碩士班

摘要

本篇論文的第一個部份描述應用在超寬頻系統中的低雜訊放大器之分析與 設計。超寬頻的低雜訊放大器需具備有寬頻、低功率、增益平坦的特性，為了達 到寬頻的目標，利用多級的概念來設計，並且選擇採用共閘級做為第一級放大， 中間兩級選擇共射級組態來提高整體增益，最後再加上一級電壓追隨器達到輸出 阻抗匹配。這個寬頻低雜訊放大器的頻寬為 2.6 ~ 8.6 GHz，增益為 16 dB ± 1dB，雜訊指數最低 5.5 dBm，消耗功率為 24 mW。 第二個部份敘述一個寬頻開關的設計與量測。這個單刀雙擲開關的頻寬為 33~60 GHz，中心頻率 46.5 GHz，介入損耗小於 4 dB，與大於 32 dB 的隔絕度。

UWB CMOS Low-Noise Amplifier

And

Wideband InGaAs pHEMT Switch

Student：Pei-Ju Chiu Advisor：Dr. Shyh-Jong Chung

Institute of Communication engineering

National Chiao Tung University

Abstract

The first part of the thesis describes the design and analysis of a low-noise amplifier for UWB system. The features of the UWB LNAs are wide bandwidth, low power consumption and flatness of gain. In order to get wide bandwidth, we utilize the concept of multi-stages to design this circuit. The first stage is a common gate topology and two common source amplifiers in the middle stages and the final stage is a voltage follower. The bandwidth of the LNA is ranged from 2.6 GHz to 8.6 GHz.

The gain is 16 dB ± 1 dB. The minimum noise figure is 5.5 dBm and the power

consumption is 24 mW.

The second part is the design and measurement of a wideband single-pole double-throw switch. The bandwidth of the SPDT switch is ranged from 33 to 60 GHz centered at 46.5 GHz. The insertion loss is less than 4 dB and the isolation is more than 32 dB.

Acknowledgements

研究所兩年的生活，除了讓我獲得專業的知識，更讓我在修養方面更上一層 樓。首先我要感謝我的指導教授鍾世忠博士，在我的研究過程中提供了充足的研 究資源，老師豐富的學識、待人處世的寬厚，讓我受益良多。同時要感謝口試委 員陳俊雄教授及郭仁財教授的不吝指導，使這篇論文更為完善。此外，要特別感 謝張志揚教授在 V-band 量測上所給予的協助。 我要感謝實驗室的成員們，在這兩年之中的幫忙以及關懷。謝謝珮華在實驗 室大大小小的事務上的處理，不辭辛勞指導我的揚育及俊甫學長，給我關懷的小 雅、明洲，經驗豐富的丹雄學長，會陪我聊天的菁偉，瘋狂變壯的侑信，常被我 問什麼時候要咪挺的佩宗，嫌肌肉不夠大的民仲，坐在隔壁一年的清文，樂觀的 嘉祐，超強的民峰，很會飆歌的鈞富，一直熄火還能考到駕照的煥能和克強。我 還要感謝從大學到現在陪伴了我六年的雅婷、怡文、佳君，謝謝你們日常生活的 關心與扶持。 最後我要感謝最支持我的爸爸、媽媽、兩個弟弟、如玉還有祈芬，謝謝你們 總是在我陷入低潮的時候給我力量，辛苦你們了。謝謝我的男友怡力總是在我最 累最需要發洩的時候陪伴著我。謝謝所有關心我的人，我的快樂均是因為你們。

Table of Contents

Abstract (Chinese)………. I Abstract (English)……….….II Acknowledgements………..……… III Table of Contents……….……… IV List of Tables……… VI List of Figures………. VII

Chapter 1 Introduction...1

1.1 Motivation...2

1.2 Organization...3

Chapter 2 Design Methodology of Low Noise Amplifier...4

2.1 Overview...4

2.2 Noise Sources...4

2.3 The basic topologies of LNAs ...4

2.4 State-of-the-art LNAs for UWB application...8

2.4.1 Broadband filter with source inductive degeneration LNA...8

2.4.2 Low noise amplifier with active input matching ...9

2.4.3 Low noise amplifier with feedback...10

Chapter 3 UWB CMOS Low Noise Amplifier ...15

3.1 Overview...15

3.2 CMOS foundry description...15

3.2 Circuit Design ...15

3.3 Simulation Results ...17

Chapter 4 Design Methodology of Broadband Switch ...23

4.1 Overview...23

4.2 Switching Devices ...23

4.3 Basic Switch Configurations...25

4.4 Broadband Switch Design...28

4.4.1 Single-Pole Single-Throw Switch...28

4.4.2 Single-Pole Double-Throw Switch...29

4.4.3 Single Pole m-Throw Switch ...29

Chapter 5 New Broadband Switches using InGaAs pHEMT...36

5.1 Overview...36

5.2 MMIC foundry description...36

5.3.1 The basic theory of broadband switch ...37 5.3.2 Circuit design...38 5.3.3 Simulated results...39 5.3.4 Measurement considerations...39 5.3.5 Measured results ...40 Chapter 6 Conclusions...48 References...50

List of Tables

Table 2.1 Comparison of wideband low noise amplifiers...14 Table 5.1 Mumford’s design tables for the maximally flat stub filters...42 Table 5.2 Tuned capacitor values for simulating a quarter-wavelength stub...43

List of Figures

Fig. 2.1 LNA topologies: (a) Resistive Termination, (b) 1 g Termination, (c) _m

Shunt-series Feedback ...11

Fig. 2.2 Inductive degeneration : (a) topology, (b) small signal model ...11

Fig. 2.3 Simplified schematic of a low noise amplifier with inductive source degeneration...12

Fig. 2.4 Simplified schematic of wideband low noise amplifier ...12

Fig. 2.5 Circuit schematic of wideband LNA with active input matching ...13

Fig. 2.6 Circuit schematic of wideband LNA with feedback...13

Fig. 3.1 The Deep N-well structure ...18

Fig. 3.2 Simplified circuit of low noise amplifier...18

Fig. 3.3 Architecture of the current mirror...18

Fig. 3.4 Layout of LNA chip...19

Fig. 3.5 S11, S22 and gain from 1 GHz ~ 11 GHz ...19

Fig. 3.6 Reverse isolation S12 from 1 GHz ~ 11 GHz ...20

Fig. 3.7 Noise figure of LNA...20

Fig. 3.8 Stability Factor, (a) K>1, (b) Mu>1...21

Fig. 3.10 The microphotograph of the UWB LNA...22

Fig. 4.1 (a) A general structure of the PIN diode; (b) ν-type, (c) π-type ...31

Fig. 4.2 Linear operational regions of a FET switch ...31

Fig. 4.3 The FET in switching configuration...32

Fig. 4.4 Complete equivalent circuit for : (a) low-impedance state (b) high-impedance state ...32

Fig. 4.5 Simplified equivalent circuit for : (a) low-impedance state (b) high-impedance state ...32

Fig. 4.6 Series-type switch configuration, (a) transmission line model, (b) equivalent circuit model...32

Fig. 4.7 Shunt-type switch configuration, (a) transmission line model, (b) equivalent circuit model………...33

Fig. 4.8 Series-shunt switch configuration, (a) transmission line model, (b) equivalent circuit model...33

Fig. 4.9 (a) The circuit of traveling wave switch, (b) Equivalent circuit of TWSW ...34

Fig. 4.10 The SPDT switch with, (a) series-type configuration, (b) shunt-type configuration ...34

Fig. 4.12 The equivalent circuit of SPmT switch for transmission state ...35 Fig. 5.1 Equivalent circuit for the maximally flat stub filter ...42 Fig. 5.2 Circuit model used for Fisher’s equivalent circuit ...43 Fig. 5.3 Summary of Fisher’s equivalence for simulating a quarter-wavelength

stub with a capacitor and its parallel tuner...43 Fig. 5.4 The equivalent circuit of SPDT switch...44 Fig. 5.5 Layout of the SPDT switch ...44 Fig. 5.6 The simulated return loss and insertion loss for the on-arm of the

33-to 60 GHz SPDT Switch...45 Fig. 5.7 The simulated return loss and isolation for the off-arm of the 33-to 60

GHz SPDT Switch ...45 Fig. 5.8 The test setups for the S parameter measurement of the SPDT switch

...46 Fig. 5.11 The measured return loss and isolation for the off-arm of the 33-to 60 GHz SPDT Switch ...47

Chapter 1

Introduction

1.1 Motivation

Ultra-wideband (UWB) radar systems were developed mainly as a military use because they could see through trees and beneath ground surface. Recently, UWB technology has been focused on consumer electronics and communications because of their potential for high-speed wireless communication. UWB is a wireless technology that transmits an extremely low-power signal over a wide spread of radio spectrum which is from 3.1 to 10.6 GHz defined by the Federal Communication Commission (FCC). Ideal goals for UWB systems are low power, low cost, high data rates. The dynamic ranges of the state-of-the-art wideband amplifiers which work well in other applications such as high-speed optical transceivers can not satisfy the UWB system specifications.

Many LNA technologies for narrow-bandwidth systems have been discussed before. Most of the topologies are designed for narrow-bandwidth systems during the last decade. Hence, it is a challenge to find an applicable LNA topology for an UWB system. A low noise amplifier which is applied to UWB systems must be characterized the wide-band input matching to a 50Ω antenna with flat gain over the entire bandwidth, minimum possible noise figure and low power consumption. In order to meet the target of system-on-chip (SOC), the digital and analog sections must be integrated together. Therefore, the CMOS technology will be adopted in this thesis.

A monolithic microwave/millimeter-wave integrated circuit (MMIC) is a microwave or millimeter-wave circuit, in which the active and passive components

are fabricated on the same semiconductor substrate such as gallium arsenide (GaAs) or indium phosphide (InP). The operating frequency is from several to hundred GHz. The GaAs pseudomorphic high electron mobility transistor (pHEMT) is the most commonly available HEMT technology. The term " pseudomorphic" comes from the fact that the device channel is generally formed from InGaAs. Making use of GaAs pHEMT technology is beneficial for performance and is able to reach the requirements of most millimeter-wave wireless applications such as local multipoint distribution system (LMDS), high speed local area networks (LAN' s), satellite communications, astronomy observations, automotive collision avoidance radar system and military use [1]. A broadband switch can be exploited for diverse applications. It controls the signal flow of the integrated circuit and it is also a crucial component to achieve the goal of SOC.

1.2 Organization

This thesis was constructed from six chapters. It was devoted to the design of an UWB CMOS LNA and a new broadband switch using InGaAs pHEMT.

Chapter 1 introduces the motivation of the research and the arrangement of this thesis.

In chapter 2, the topologies in common use of LNA will be introduced. Each of them has different advantages with different design architectures. We will make a description for the four kinds of different topologies and choose the most suitable one for wideband applications. In addition, the survey of recent low-noise amplifiers will also be listed in this chapter.

In chapter 3, a LNA whose bandwidth ranges from 2.6 GHz to 8.6 GHz will be

presented. The architecture uses 1

m

achieve wideband performance, we introduce some gain matching components at the third stage. The simulated results will be listed in the end.

In chapter 4, the design methodology of broadband switches and various switching devices will be introduced, and switch configurations will also be presented.

In chapter 5, the design theory and the design flow of a SPDT switch will be introduced here. The bandwidth of the switch is ranged from 33 GHz to 60 GHz. The simulated and measured results will be listed in the last.

In the last chapter, we will make the summary and indicate some suggestions for the future design.

Chapter 2

Design Methodology of Low Noise Amplifier

2.1 Overview

This chapter is composed of three sections; first, simple description of CMOS foundry will be listed. Second, noise sources and four basic topologies of low noise amplifiers will be discussed in detail. Finally, we will discuss the state of the art for UWB LNAs.

2.2 Noise Sources

The output noises are mainly come from thermal noises. Besides the thermal noise of resistances (i_{n R,} ), there are the thermal noise of the channel current (i_{n d,} ) and

the gate induced current noises (i_{n g,} ) [2]. They are listed below: 2 , 1 4 n R i kT f R = ∆ (2.1) 2 , 4 0 n d d i = kT gγ ∆ (2.2) f 2 2 2 , 0 4 gs n g d C i kT f g ω β = ∆ (2.3) where g is zero bias conductance, γ is the channel noise factor, and β is the gate _d0

induced current noise factor.

2.3 The basic topologies of LNAs

For the LNA circuits, a resistive impedance matching between the LNA and the driving source is a critical requirement. It is difficult to provide good impedance

matching to the source without degrading the noise performance because the input of the LNA circuits is connected to a capacitive node. There are various matching methods that have been applied to improve LNA performance. On the basis of these matching methods, the LNA topology can be sorted by four kinds [3]:

Resistive Termination The 50Ω resistance is connected to the input node of a

common source amplifier directly and the architecture is shown as Fig. 2.1(a). The connection means that the input source can see only the resistor over reasonable broadband. Nevertheless, the resistance which is connected directly to the input terminal weakens the signal ahead of the transistor and brings thermal noise of its own. This topology is rarely used in the LNA design because of its unacceptable high noise figure.

1/g Termination The input impedance is set by the 1/_m g of the transistor in _m

the common gate stage shown as Fig 2.1(b). This architecture is very simple and can easily achieve the appropriate impedance matching. This topology seems to be a good choice for a wide bandwidth system because the transistor’s g is merely affected _m

in the frequency range of UWB system. In order to make 1/g =50Ω, the value of _m

m

g has to be fixed at 20mS. This means that the transistor size has to be fixed and this will affect the noise figure of the single transistor system. The gain of this LNA is also fixed without increasing output resistance. Therefore, there will be more than one stage when using this type topology to enhance the overall gain.

In the common gate configuration, the noise figure and the matching circuits totally depend on the single transistor in the common gate stage. The equation 2.1 shows the noise figure of the single transistor [3].

α γ

+ = 1

F (2.1)

0 d m g g = α (2.2)

where g is the transconductance and _m g is the zero bias drain conductance. For _d0 the long channel device, γ equals to 2/3 and α equals to 1. For the short channel case, the value of γ is greater than 2/3. Based on these data, the best noise figure of this 1/g termination topology tends to be more than 2.2dB. Consequently, this topology _m can afford quite wide bandwidth impedance matching but bring a large noise figure and is difficult to achieve high gain performance.

Shunt-Series Feedback The architecture is shown as Fig. 2.1(c). With the shunt

series feedback architecture, the bias point of the input is fastened with the output voltage. For this reason, the biasing point of this system is not set to the optimal bias point. This will cause an extra power consumption to achieve the desired gain. Moreover, the shunt series feedback architecture has a stability problem.

Usually the shunt series feedback can be analyzed as equation 2.3.

⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ + − + − + − ∆ = S m m f S m f m S m m f R g Z g Z R R g R g R g Z g Z R 1 ) 1 1 ( 2 2 1 1 [S] 0 0 0 0 _(2.3) where S m m f R g Z g Z R + + + = ∆ 1 2 0 0

. From the S-parameter matrix, the ideal matching condition is S₁₁ = S₂₂ =0, the series resistance R can be calculated as _S

m f S g R Z R 1 2 0 ₋ = . (2.4)

Substituting 2.4 in to 2.3 attains S-parameter

⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ − + ∆ = 0 1 0 1 [S] 0 0 0 Z R Z R Z f f _{. (2.5)}

S

R , we can achieve the goal of very wide bandwidth and flat gain. The only

restriction of this architecture is that the source resistance R must be nonnegative. _S

If R becomes negative the system will oscillate. This limitation puts bounds to the S

value g of the transistor with desired gain _m S . ₂₁

0 21 2 0 min 1 Z S Z R g g_m ≥ _m = f = − (2.6)

Therefore a transistor satisfying the condition of equation 2.6 can be selected in the negative feedback configuration. This analysis is only valid for low frequencies where all reactance components can be neglected. In the case of UWB systems, the parasitic capacitance and inductance can not be neglected. Because of the undesired effects of parasitic, not only the gain degradation but also the noise figure raising will happen at high frequency. Besides, the stability drops to the unstable region because of the feedback effect. This type of configuration must improve its gain and noise figure at high frequency without reducing stability.

With this configuration, it requires very high power consumption to increase the gain because the bias point of the system is fixed at the output voltage, which is not the optimal DC biasing point. However, the architecture gives wide bandwidth characteristic for the UWB system.

Inductive Degeneration The last topology is displayed in the figure 2.2(a).

From the small signal model shown as Fig. 2.2(b), the input impedance of this architecture can be calculated as

S gs m gs g S L C g sC L L s( ) 1 ( ) Z_in = + + + (2.7) At the resonant frequency, the input impedance is purely real and proportional to L . _S Therefore, this system don’t have to add additional any resistive components and it can reach the input impedance matching by choosing appropriate value of the L . _S This leads to a very good noise figure and impedance matching for a narrow

bandwidth system. However, since this topology utilizes resonance at the desired frequency, it can be used only for narrow bandwidth signals and it is not suitable for wide bandwidth applications.

2.4 State-of-the-art LNAs for UWB application

Recently, there are several low-noise amplifiers designed for UWB systems. The general architectures can be sorted for three kinds; one is choosing an inductive degeneration topology which a broadband filter is located in front of. The second is selecting a common gate topology as the first stage in addition to more stages to enhance the power gain and the bandwidth and the third is using a shunt-series feedback configuration. Even though the first kind makes use of inductive degeneration which can afford lowest noise figure, this architecture also utilizes many passive components which will introduce higher noise figure. The second kind utilizes common gate architecture to achieve input matching, but it usually has more than 1 stage and leads to more power consumption. Low noise figure and power consumption are two important features in UWB system. The third kind uses feedback to enhance the bandwidth but this will lead to the problem of stability. In order not to lead the circuit to unstable, the value of resistor must be chosen carefully. The disadvantage of the feedback topology is that the circuit is very sensitive to the process variation of the foundry. If the circuit was designed near the boundary of the stable circle, the circuit will introduce oscillation even with little process errors. It seems that there is no perfect design of low-noise amplifiers for UWB systems so far.

2.4.1 Broadband filter with source inductive degeneration LNA

In September 2001, Pietro Andreani and Henrik Sjoland published a method to optimize noise of inductively degenerated CMOS low-noise amplifier [4]. The

simplified schematic is shown in Fig. 2.3. They mainly discussed the relationship between Q, channel noise and gate induced current noise. When the value of Q is increasing, the channel noise decreases but it also leads the gate induced current noise to increase. The capacitor C has the function of decoupling Q from _d C , which _gs

allows for an adjustable reduction of Q for any given value of C . This architecture _gs

is only suitable for narrow band application. In 2004, this circuit was improved for wide-band use. Andrea Bevilacqua and Ali M Niknejad added two inductors (L L₁, ₂)

and capacitors (C C1, 2) in front of the previous circuit as shown in Fig. 2.4. These

passive components form a three-section band-pass filter to resonate its reactive part over the whole band. In this way, it can achieve the wideband input impedance matching. Its 3 dB bandwidth ranges form 2.4 to 9.5 GHz and power consumption is 9 mW [5].

2.4.2 Low noise amplifier with active input matching

This architecture utilizes the characteristic of common-gate topology to achieve the input impedance matching. A circuit presented in 2004 is shown as Fig. 2.5. The resistance looking into the source terminal is 1 g and proper choice of bias current m

can get the desired 50Ω. The second stage uses a feedback topology to enhance the bandwidth and increase total gain. The addition of L makes more gain and it do not f

lead the circuit to oscillate. At some frequencies, the phase of output voltage is in-phase with input voltage (positive feedback). L can also avoid this situation to _f

happen. The capacitance C blocks the DC current that comes from the output node. _f

The bandwidth of this circuit ranges from 3.1 to 6.1 GHz and its gain is around 17 to 15.5 dB [6].

2.4.3 Low noise amplifier with feedback

A shunt-series feedback topology LNA schematic is shown in Fig. 2.6. In the figure, the load inductance L2 substitutes for the resistive load of the original

configuration. The impedance of the inductor increases as the frequency increases and this can compensate for the amplifier degradation at high frequency. The inductor L1

is added for additional gain boost at high frequency. The C is used for DC blocking. f

This capacitance blocks the DC current that comes from the output node. The transduced gain is 8.5 dB and has a variation of ± 0.2 dB. The noise figure is 3 dB [7].

We make a table to compare some wide-band LNAs shown in Table 4.1. Input 1dB compression point and IP3 are merely concerned in case of UWB LNA because in general the transmit power is limited to be less than -42dBm/Hz.

(a) (b)

(c)

Fig. 2.1 LNA topologies: (a) Resistive Termination, (b) 1 g Termination, (c) _m

Shunt-series Feedback

(a) (b) Fig. 2.2 Inductive degeneration : (a) topology, (b) small signal model

Fig. 2.3 Simplified schematic of a low noise amplifier with inductive source degeneration.

Fig. 2.5 Circuit schematic of wideband LNA with active input matching

[5] measured [6] Simulated [7] Simulated This work Simulated

Technology 0.18 um CMOS 0.18 um CMOS SiGe 0.5 um 0.18 um CMOS

Band (GHz) 2.4 to 9.5 3.1 to 6.1 0.8 to 1.6 2.6 to 8.6 Bandwidth 7.1 (3dB) 3 0.8 6 S11 (dB) <-9.4 -12.9 to -18 N/A <-9.4 S21 (dB) 10.4 (max) 17 to 15.5 8.5 ± 0.2 17.6 to 15.6 S12 (dB) <-35 <-43 N/A <-44.5 NF (dB) 4.2 to 8 3.9 to 4.3 about 3 5.58 to 6.6 Power (mW) 9 21 23.1 24 Area( 2 mm ) 1.1 1.86 x 1.36 N/A 1

Chapter 3

UWB CMOS Low Noise Amplifier

3.1 Overview

This chapter will present a 2.6-to-8.6 GHz low-noise amplifier using a 0.18 um CMOS process. It is based on the analysis in chapter 2. The foundry description, design and simulation of the circuit will be shown in the following.

3.2 CMOS foundry description

The CMOS device used in this design is fabricated by TSMC Semiconductor Corporation with a deep N-well 0.18-um process, and the Deep N-Well structure is shown as Fig. 3.1. This CMOS process provides academic users only as it is fabricated through TSMC provided shuttle. It possesses 1 poly layer and 6 metal layers with low k inter-metal dielectric. Deep N-well, MiM capacitor, high poly resistor, multi-Vt device and thick top metal are available for 1.8V/3.3V applications. It is suitable for logic, mixed signal, and RF designs [8].

3.2 Circuit Design

In order to achieve the wide-band input impedance matching and flat gain, I utilize the multistage architecture. Using multistage architecture can expand the overall bandwidth [9]. There are 4 stages in this circuit totally, as shown in Fig. 3.2. First stage is a common gate structure in order to achieve the impedance match of

50Ω. The input impedance is close to 1 g and m g is not much affected by m

second common source structure is for gain boost. The third source inductive degeneration cascade architecture can not only enhance the gain but also reinforce the reverse isolation. Reverse isolation is a crucial factor because LNA is often put in front of mixer. In order to avoid the local oscillator leaking back to the LNA, it’s better to choose a LNA with good reverse isolation for systems. The final stage is just used as a buffer to permit the output impedance to be dropped to around 50Ω.

The first and final stages utilize two current sources to bias the circuit, so the current mirrors should be integrated into the circuit. The design of the current mirror is same as tradition except for the capacitor Cblock, as shown in Fig. 3.3. This

capacitor can block the high frequency interference which is leaking from the drain node. If this capacitor was removed, the noise figure of the system will arise significantly.

Because we utilize common gate as the first stage, the thermal noise of channel current has a significant effect on system’s noise figure. In order to minimize the effect, we have an analysis for the relationship between ∆V, Ibias and

2 , n d i where gs t V V V ∆ = − . 2 , 4 0 n d d i = kT gγ ∆ (3.1) f 2 2 2 , , m n in n d g V =i (3.2) 2 , 2 3 n i bias kT V V I γ = ∆ (3.3) Therefore, we can reduce the noise figure by decreasing ∆V and increasing I_bias.

The drain bias voltage is 1.8 V and the gate bias voltage is 0.7 V. The bias voltage of current mirrors is adjustable in the range of 0 to 1.8 V. The layout of this low-noise amplifier is accomplished by the Cadence tools and is depicted in Fig. 3.4.

The chip size is 1 x 1 2

3.3 Simulation Results

The model used in this simulation is BSIM3v3 provided by the foundry. The performance of the low-noise amplifier is simulated with the commercial CAD software Advanced Designed System. The post-simulation are performed via a full-wave EM full-wave simulator SONNET.

The simulated gain and input, output return loss is depicted in Fig. 3.5. The reverse isolation is shown in Fig. 3.6. The minimum noise figure is 5.6 dB, as shown in Fig. 3.7. The total bandwidth is from 2.6 GHz to 8.6 GHz. The gain is 16dB ± 1 dB and input/output return loss are better than 10 dB. The reverse isolation is better than 44 dB. The stability factor K and Mu are also simulated, as shown in Fig. 3.8(a) and (b). The sufficient conditions for unconditional stable are K>1 and Mu>1 of two ports network.

The output power versus input power is simulated at 5.5 GHz, as shown in Fig. 3.9. The 1 dB compression point was -27 dBm at 5.5 GHz.

Fig. 3.1 The Deep N-well structure

Fig. 3.2 Simplified circuit of low noise amplifier

Fig. 3.4 Layout of LNA chip

Fig. 3.6 Reverse isolation S12 from 1 GHz ~ 11 GHz

(a) (b) Fig. 3.8 Stability Factor, (a) K>1, (b) Mu>1

Chapter 4

Design Methodology of Broadband Switch

4.1 Overview

A switch can be applied to execute the multiple accesses, which is widely used and considered as a main choice in communication. It also reduces the duplicate of the circuits with the same functions. In low frequency range, the design of switches neglects the parasitic and transmission-line effects. On the contrary, these effects occur significantly in the millimeter-wave frequency range and must be taken into account in the switch design. This chapter has a full discussion on the design methodology of broadband switches.

4.2 Switching Devices

PIN diodes and FETs are two types of devices used commonly in the control circuits. Here, we discuss the significant properties of these devices.

PIN Diodes A PIN diode is a pn junction device that has a very minimally

doped or intrinsic region located between the p-type and n-type contact regions as illustrated in Fig. 4.1(a). The combination of the intrinsic or i-region results in characteristics that is very advantageous for certain device applications. In reverse bias the intrinsic region causes very high value for the diode breakdown voltage, whereas the device capacitance is reduced by the increased separation between the p- and n-region. In forward bias the conductivity of the intrinsic region is controlled by the injection of charge from the end regions. A practical PIN diode consists of a lightly doped p- or n-region between the highly doped p-type and n-type contact

region, as shown in Fig. 4.1(b) and Fig. 4.1(c). To identify very lightly doped p and n material, the Greek letters are used; consequently, lightly doped p material is called π-type and lightly doped n material is called ν-type. The diode is a resistor controlled by bias current with preferable linearity and low distortion. PIN diodes can provide faster switching speed and can handle medium to large RF power levels. They also make excellent RF switches, phase shifters and limiters. Sometimes the Schottky barrier diode (SBD) is applied for faster switching speed.

FETs In recent years PIN diode switches have been increasingly replaced by

FETs based monolithic switches, especially for low to medium power applications. The FET switches are three-terminal devices, in which the gate bias V controls the _g

states of the switch. The FET acts as a voltage controlled resistor, where the gate bias controls the drain-to source resistance in the channel. The intrinsic gate-to-source and gate-to-drain capacitances and device parasitics limit the performance of the FET switches at higher frequencies. In switching applications, a low-impedance (nearly short) state is obtained by making the gate voltage equal to zero. When the negative gate-source bias is larger than the pinch-off voltage in magnitude, the FET is in a high-impedance (nearly open) state. Fig. 4.2 shows the linear operation regions of a switching FET [10]. The configuration of a switching FET [11] is indicated as Fig. 4.3.

A low-impedance state can be adequately modeled by a resistance (R ) which is _on

series connection to a parasitic inductor (L ) between the source and the drain as on

depicted in Fig. 4.4(a). A complete equivalent circuit in a high-impedance state is illustrated in Fig 4.4(b). The equivalent circuit is based on the device geometry from the reference [10], [12]. The off-state drain-to-source leakage resistance (R ) is _ds

generally large enough to be neglected in circuit modeling. The drain and the source are directly capacitive-coupled and through the gate (C ,_ds C and _gs C ). All of these _gd

capacitances have series parasitic resistive elements (R and gs R for gd C and gs

gd

C , R for _d C ). A simplified FET model can be used without sacrificing accuracy _ds

as shown in Fig. 4.5(a) and Fig. 4.5(b). The parasitic inductor was neglected for the on-state equivalent circuit. The off-state equivalent circuit has been reduced to a simple series resistor (Roff ) and a capacitor (Coff ). For the simplification, it is

assumed that the magnitudes of the reactances of the various capacitances are much greater than the various parasitic resistances. This assumption yields the following relationship: 2 2 [1 ] [1 ] gs gd s d off ds gs gd gs gd ds R R R R R C C C C C C + + = + + + + + (4.1) 2 2 1/( ) 1/ 1/ [1 ] [1 ] gs gd ds off ds gs gd gs gd ds C C C C C C C C C C + ≈ + + + + + (4.2)

Note that the relationships for R and _off C_off are frequency independent. The

frequency dependent terms have been ignored. It is important to note that no DC power is required by the FET switches in either state. The other advantage of FET switches is that additional bias circuits are unnecessary because of the DC isolation between gate and drain (or source) by constitution. The FET switches are superior to the PIN diode switches because they don’t have DC power consumption and DC biasing isolation.

4.3 Basic Switch Configurations

There are two basic configurations [13] that can be used for a simple switch design to control the flow of millimeter-wave signals along a transmission line. One is series-type switch and the other is shunt-type switch. The third configuration that

consists of the series-type and shunt-type switches is called series-shunt switch.

Insertion loss and isolation are two measures of the performance for the switch when it is on-state and off-state. Insertion loss is defined as the ratio of the power delivered to the load in the on-state of the ideal switch to actual power delivered by the practical switch. It is usually expressed in decibels. Isolation is defined as the ratio of the power delivered to the load for an ideal switch in the on-state to the actual power delivered to the load when the switch is in the off-state.

Series-type Switches The equivalent circuit of a series-type switch is shown

as Fig. 4.6(a). The low-impedance state of the FET allows the signal to propagate, while in the high-impedance state, the incident power on the switch is mostly reflected back. The low- and high-impedance states of the FET are called on-state and off-state for a series-type switch. The insertion loss may be calculated by considering the equivalent circuit depicted in Fig. 4.6(b). If V_L denotes the actual voltage across

the load in the ideal switch, the insertion loss can be written as

2 2 2 0 0 0 1 1 1 4 4

low low low L LD R R X V IL V Z Z Z ⎛ ⎞ ⎛ ⎞ = = + + _{⎜ ⎟} + _{⎜ ⎟} ⎝ ⎠ ⎝ ⎠ , (4.3)

where Zlow =Rlow+ jXlow is the impedance of the switching device in the

low-impedance state. Similarly, the isolation is given as

2 2 2 0 0 0 1 1 1 4 4

high high high L LD R R X V ISO V Z Z Z ⎛ ⎞ ⎛ ⎞ = = + + _{⎜ ⎟} + _{⎜ ⎟} ⎝ ⎠ ⎝ ⎠ , (4.4)

where Zhigh =Rhigh+ jXhigh is the impedance of the switching device in the

high-impedance state.

Shunt-type Switches Fig. 4.7(a) illustrates the equivalent circuit of a

shunt-type switch. The shunt-type switch is complementary to the series-type switch. The low-impedance state of the FET almost reflects the incident power back and the

high-impedance state permits the signal to propagate. Therefore, the low- and high-impedance states of the FET are called off-state and on-state for a shunt-type switch. The insertion loss may also be derived from the equivalent circuit as shown in Fig. 4.7(b). If VL denotes the actual voltage across the load in the ideal switch, the

insertion loss can be written as

2 2 2 0 0 0 1 1 1 4 4

high high high L LD G G B V IL V Y Y Y ⎛ ⎞ ⎛ ⎞ = = + + _{⎜ ⎟} + _{⎜ ⎟} ⎝ ⎠ ⎝ ⎠ , (4.5)

where Y_high =G_high+ jB_high is the admittance of the switching device in the

high-impedance state. Similarly, the isolation is given as

2 2 2 0 0 0 1 1 1 4 4

low low low L LD G Y B V ISO V Y Y Y ⎛ ⎞ ⎛ ⎞ = = + + _{⎜ ⎟} + _{⎜ ⎟} ⎝ ⎠ ⎝ ⎠ , (4.6)

where Ylow =Glow+ jBlow is the admittance of the switching device in the

low-impedance state.

Series-Shunt Switches The simplest series-shunt switching configuration is

indicated in Fig. 4.8(a). This switching circuit can be analyzed in terms of the equivalent circuit as shown in Fig. 4.8(b). For on-state, the impedance of the device

se

Z is denoted by the low impedance Z_low, and the impedance Z is denoted by the _sh

high impedance Zhigh. From the simple circuit analysis, the insertion loss can be

written as 2 0 0 0 ( )( ) 1 2 2 high low high Z Z Z Z IL Z Z + + = + . (4.7) Similarly, the isolation is written as

2 0 0 0 ( )( ) 1 2 2 low high low Z Z Z Z ISO Z Z + + = + . (4.8) If the non-identical devices are used in the series and the shunt locations, the values of

high

Z and Z_low in (4.7) will be different from those in (4.8).

In general, the isolation obtained by using the series-shunt configuration is much better than that for either the series-type or the shunt-type switch. The insertion loss for the series-shunt configuration is worse than that for a shunt-type switch but better than that for a series-type switch.

4.4 Broadband Switch Design

4.4.1 Single-Pole Single-Throw Switch

A single-pole single-throw (SPST) switch is used to control the flow of signals along a transmission line. As mentioned previously, three configurations can be applied to design a SPST switch. In the millimeter-wave frequency range, the device paracitics introduce more significant detrimental effects on insertion and isolation performance. Some well-known compensated techniques, such as capacitive [14] or impedance-transformation methods [15], can be exploited to minimize the non-ideal open or short effects. A traveling-wave concept was also applied in SPST switch design.

A traveling-wave switch (TWSW) whose bandwidth is ranged from DC to 110 GHz has been published in May, 2000[16]. The circuit is shown as in Fig. 4.9(a). The TWSW is described as the combination of a distributed shunt FET and a transmission line of drain electrode. The reason that the switch can have a very wide bandwidth is the equivalent circuit, as shown in Fig. 4.9(b), is the same as a lossy transmission line for the on-state of the TWSW. This architecture is only suitable for single-pole single-throw switch design because that when two or more branches combine together, the traveling-wave property, i.e wideband performance, will be destroyed.

4.4.2 Single-Pole Double-Throw Switch

The series-type and shunt-type circuits for single-pole double-throw (SPDT) switch is illustrated in Fig. 4.10(a) and Fig. 4.10(b). The switch requires at least two switching devices. If the branch of the series-type is ON state, the FET is biased in the low-impedance state, and the branch is OFF state while the FET is biased in the high-impedance state. If the branch of the shunt-type is ON state, the FET is bias on the high-impedance state, and vice versa. The input signal flow controls by reversing the FET states. The bandwidth of the shunt-type SPDT switch is limited because of the quarter-wavelength transmission line, which is required between the locations of the two switching devices.

The SPDT circuit, as shown in Fig. 4.11, has the bandwidth of 8 GHz which is ranged from 56 to 64 GHz with insertion loss less than 3.2 dBm [17]. The structure is similar with the circuit illustrated as section 4.4.1. The switch is composed of the quarter-wavelength transformer and the FETs which are spaced by one quarter wavelength between the devices and the common joint. The bandwidth of this SPDT switch is limited by the quarter-wavelength transformer but the transformer can provide high isolation and minimize the loading effect. In spite of the circuit seems like the TWSW, it doesn’t have the characteristic of traveling wave so its bandwidth is not wide as the traveling-wave switch.

4.4.3 Single Pole m-Throw Switch

The single-pole m-throw (SPmT) switch has a single input, and m arms output and only one arm of them is on state. This kind of switch can be used to control antenna wave beams that the most common application is anti-collision radar used in car. A SPmT shunt-type switch can be realized by using the short-circuited stub filter

which will be introduced in chapter 5. The FETs are spaced by m quarter wavelength transformers whose characteristic admittance is Y between the joint of the input and ₀

the m output arms. Each arm has n short-circuited stubs located between FETs and the characteristic admittance of each stub is Y_TN. The (m-1) off-arms have a nearly short

circuit made by the low-impedance FETs. The equivalent characteristic admittance of these (m-1) arms is (m-1)Y . The equivalent circuit of the whole switch, as shown in ₀

Fig. 4.12 [18], will be looked like a short-circuited stub whose characteristic admittance is (m-1)Y shunt with the ON output arm. The entire characteristic is still ₀

hold with the theory of the short-circuited stub filter. For this reason, the bandwidth is unrestricted by utilizing this design approach.

(a)

(b) (c)

Fig. 4.1 (a) A general structure of the PIN diode; (b) ν-type, (c) π-type

Fig. 4.3 The FET in switching configuration

(a) (b) (a) (b) Fig. 4.4 Complete equivalent circuit for :

(a) low-impedance state (b) high-impedance state

Fig. 4.5 Simplified equivalent circuit for : (a) low-impedance state

(b) high-impedance state

(a)

(b)

Fig. 4.6 Series-type switch configuration, (a) transmission line model, (b) equivalent circuit model

(a)

(b)

Fig. 4.7 Shunt-type switch configuration, (a) transmission line model, (b) equivalent circuit model

(a)

(b)

Fig. 4.8 Series-shunt switch configuration, (a) transmission line model, (b) equivalent circuit model

(a)

(b)

Fig. 4.9 (a) The circuit of traveling wave switch, (b) Equivalent circuit of TWSW

(a)

(b)

Fig. 4.10 The SPDT switch with, (a) series-type configuration, (b) shunt-type configuration

Fig. 4.11 Circuit diagram of the FET T-R switch

Chapter 5

New Broadband Switches using InGaAs pHEMT

5.1 Overview

In this chapter, a SPDT switch whose bandwidth is ranged from 33 to 60 GHz will be presented. It is based on the Mumford’s and Fisher’s theory that will be described later. The fabrication, design process and simulated results will be presented in the following. The SPDT is an extended concept of the SPST switch, so these results will be compared with the SPST switch which was designed by Y. Y. Chen [18]. The measurement considerations are also stated in detail. The measured data will be listed in the last.

5.2 MMIC foundry description

This SPDT switch is fabricated by WIN Semiconductor Corporation with a standard 0.15-um high-power InGaAs pHEMT MMIC process. The process uses a hybrid lithographic approach which includes direct-write electron beam (E-beam) lithography for sub-micron T-gate definition and optical lithography for the other process steps. The pHEMT devices are grown using molecular beam epitaxy (MBE) on 6-inch semi-insulating (SI) GaAs substrates. The pHEMT device has a typical unit

current gain cutoff frequency ( f ) of 85 GHz and maximum oscillation frequency _t

( f_max) of 200 GHz. The peak DC transconductance (G ) is 495 _m mS mm when

gate-source voltage is -0.45 V. The gate-drain breakdown voltage is 10 V, and the

maximum drain current is 650 mA mm when gate-source voltage is 0.5 V. This

mesa-resistor (epitaxial layer), metal-insulator-metal (MIM) capacitors, spiral inductors and air bridges. The thickness of the wafer is 100 um for the backside metal plating and reactive ion etching (RIE) via-holes are used for DC grounding.

5.3 Broadband Switches Design

5.3.1 The basic theory of broadband switch

W. W. Mumford [19] published a design approach of a maximally flat filter. The filter, which is illustrated in Fig. 5.1, consists of the quarter-wavelength short-circuited stubs spaced by quarter wave-length distance. The characteristic admittance of each short stub can be examined by the table, is shown in Table 5.1, created by Mumford. The filters are symmetrical and only the normalized admittance are listed.

In 1965, R. E. Fisher [20] has suggested that the diode capacitance and its parallel resonating stub tuner could be analyzed approximately as a simple stub. J. F. White [21] demonstrated the feasibility of Fisher’s equivalence for low frequencies from 1 to 2 GHz in 1968. In this thesis, Fisher’s equivalence is also adopted except that the switching devices are replaced by the FETs and the frequencies are extended to the millimeter-wave frequency range.

The thesis of Fisher states that when the length of a transmission line whose admittance is YE is quarter wavelength, it can be replaced by a diode capacitance C

shunted with a transmission line whose admittance is YT and phase delay is θ . The T

circuit model used for Fisher’s equivalent circuit is shown in Fig. 5.2. The following gives the relationship between YE, YT, θ and the diode capacitance C. T

2 1 0 0 0 2 cot 1 E T T T C C Y C Y Y Y ω ω ω π − ⎧ _{⎡ ⎛ ⎞⎤}⎡ _{⎛ ⎞} ⎤⎫ ⎪ _{⎢ ⎥}⎪ = _⎨ + _{⎢ ⎜ ⎟⎥} +_{⎜ ⎟ ⎬} ⎢ ⎥ ⎝ ⎠ ⎝ ⎠ ⎣ ⎦ ⎪ _{⎣ ⎦}⎪ ⎩ ⎭ (2.9)

Fig. 5.3 is the plot for Y_Tand θ_T versus 0 E C

Y

ω _{. For a more accurate estimation,}

some corresponding variable values for the common steps in the estimation of

0 E C

Y

ω _{are listed in Table 5.2. If the diode capacitance C is zero which means the}

capacitance is not used, in other words the normalized susceptance 0 E C

Y

ω _{is zero,}

the phase delay and normalized admittance T

E Y

Y of the required tuning stub is

90° and 1. The reason is that the phase delay of a quarter wavelength transmission line is 90°. This thought is instinctive. The largest allowable value of 0

E C

Y

ω _is

4

π _{. To look into the curves,} T E Y

Y and θT are both zero when 0 E C

Y

ω

is 4π . Combined the Mumford’s and Fisher’s theories, we can get the preliminary circuit of the switch. The equivalent circuit is shown in Fig. 5.4. The circuit structure is suitable for the design of the SPST switch, SPDT switch and even SPmT switch because all the off output arms can be simplified as short-circuited stubs with proper characteristic admittances. This speciality leads to keep the structure as the maximally flat filter, so the bandwidth will be unlimited by the quarter wavelength transformer.

5.3.2 Circuit design

The microstrip transmission line is used for the design of the circuit. The switching device is made by InGaAs pHEMT process whose gate width is 2 x 100 um. This SPDT utilizes two SPST switches [18] to shunt together. The SPST switch is composed of four short-circuited stubs and four transistors so it is called 4-order switch. Each of the transistors is shunt with a short-circuited stub and is spaced by quarter wavelength. The gate of each transistor is connected with a thin-film isolation

resistor R . For the sake of isolating the noise to come into gate, the value of iso R iso

is chosen as large as possible , here we select it to be 2 KΩ. The gate control voltage (V ) is set to be -2V for the high-impedance state and 0V for the low-impedance state. g

In order to verify the bandwidth of SPDT switch has relation to the 4-order SPST switch, we have to design a 3-order SPDT switch. The reason is that the off arm can be equivalent to a short-circuited stub and this leads the on arm to be looked like a four-order SPST switch. The layout of the SPDT switch is achieved by Cadance tools

with chip size 2 x 2 2

mm , as shown in Fig. 5.5.

5.3.3 Simulated results

The switching pHEMT model for this simulation is a HP EEsof scalable nonlinear HEMT model (EE_HEMT model) provided by the foundry. The S-parameters and harmonic balance techniques are simulated by Applied Wave Research (AWR) Microwave Office. The high frequency behavior was confirmed by the commercially available electromagnetic (EM) simulator SONNET.

The simulated insertion loss and return loss of ON-state from 20 GHz to 70 GHz is plotted in Fig. 5.6. The minimum insertion loss is -2.68 dB, and the bandwidth is defined in the range that the insertion loss is less than 4 dB. Therefore, the bandwidth is from 33 GHz to 60 GHz. The return loss is larger than 9.6 dB. The simulated isolation and return loss of OFF-state is illustrated in Fig. 5.7. The isolation is better than 32.7 dB and the output return loss is less than 2.7 dB. The total bandwidth is centered at 46.5GHz for a flat insertion loss.

5.3.4 Measurement considerations

includes of Q-band, V-band, the parasitic effect of the bonding wire is very significant. Therefore, we have to perform on-wafer measurement. The location of probe can’t be arbitrarily placed without concern with the probe station. Each side of the probe station can only put one probe to ensure every probe having space to move. Because the SPDT switch has three ports, one for input and the other two is for out puts, there must be a right angle appeared in the layout. As a result, the calibration process will not be the same as usual. The ideal approach is to measure it via a vector network analyzer (VNA) which has more than three ports. Then, put the probe to a calibration kit which can be used to calibrate three ports and whose size is similar to the DUT. Because there is a 90∘ bend between three ports, it is hard to have a perfect through line. What mention above is difficult to achieve, so we use another method to measure it. Although this will make some inaccuracy, it is acceptable. The approach to this problem is to complete the 2 ports Through-Reflect-Line (TRL) calibration process. After that, move one probe to the side of input port and the other locates on the original side which is the same direction as output port. The 3rd port (also is output port) is terminated with 50Ω termination. Although this method may induce slightly inaccuracy, it is quite acceptable.

5.3.5 Measured results

The SPDT switch was measured via on-wafer probing. Fig. 5.8 presents the test setup used for the circuit measurement. There are 5 pads in the SPDT layout. Two are connected to control bias and one is for 50Ω termination, the other two are connected to the Vector Network Analyzer. The micro-photograph of the SPDT switch is shown in Fig. 5.9.

The control bias voltage is 0 V for the off-state and -2 V for the on-state. The measured insertion loss, input and output return loss of the on-arm is plotted in Fig.

5.10. The insertion loss is less than 4 dB and input and output return loss is better than 10 dB within 33 GHz to 55 GHz. The off-arm isolation, input and output return loss is illustrated in Fig. 5.11. The isolation is better than 30 dB from 30 to 70 GHz. It has 22 GHz bandwidth centered at 44 GHz for a flat insertion loss.

Fig. 5.1 Equivalent circuit for the maximally flat stub filter 1 0

Y Y

Y Y

_{2 0} 0.100 0.200 0.300 0.600 0.500 1.000 0.700 1.400 1.000 2.000 1.400 2.800 2.000 4.000 2.500 5.000 Thr ee S tubs 3.000 6.000 0.100 0.292 0.200 0.571 0.400 1.109 0.800 2.141 1.300 3.395 1.900 4.877 Four S tubs 3.000 7.568 1 0

Y Y

Y Y

_{2 0}

Y Y

_{3 0} 0.100 0.366 0.532 0.200 0.694 0.989 0.300 1.005 1.410 0.400 1.304 1.808 0.500 1.596 2.193 0.700 2.166 2.933 0.900 2.724 3.648 1.300 3.819 5.038 2.000 5.702 7.403 Five S tubs 2.800 7.829 10.058

Fig. 5.2 Circuit model used for Fisher’s equivalent circuit 0

C Y

E

ω

Y Y

_{T E}

θ

_T(degree) 0.000 1.000 90.0 0.100 0.985 84.2 0.200 0.956 78.4 0.300 0.915 71.8 0.400 0.850 64.8 0.500 0.760 56.7 0.600 0.627 46.2 0.700 0.436 31.9 0.750 0.300 21.8 0.780 0.120 8.75 0.7854( 4)π 0.000 0.00 Fig. 5.3 Summary of Fisher’s equivalence for

simulating a quarter-wavelength stub with a capacitor and its parallel tuner

Table 5.2 Tuned capacitor values for simulating a quarter-wavelength stub

T

Fig. 5.4 The equivalent circuit of SPDT switch

Fig. 5.6 The simulated return loss and insertion loss for the on-arm of the 33-to 60 GHz SPDT Switch

Fig. 5.7 The simulated return loss and isolation for the off-arm of the 33-to 60 GHz SPDT Switch

Fig. 5.8 The test setups for the S parameter measurement of the SPDT switch

Fig. 5.10 The measured return loss and insertion loss for the on-arm of the 33-to 60 GHz SPDT Switch

Fig. 5.11 The measured return loss and isolation for the off-arm of the 33-to 60 GHz SPDT Switch

Chapter 6

Conclusions

In this thesis, two integrated circuits are presented. One is using WIN InGaAs pHEMT and the other is using TSMC 0.18 um CMOS process.

A low-noise amplifier whose bandwidth is 2.6 GHz to 8.6 GHz is represented in Chapter 3. The gain of the LNA is 16 dB ± 1dB. The system’s minimum noise figure is 5.58 dB at 3.5 GHz. The analysis of the noise figure is based on the existing analytical methods which are suitable for narrow bandwidth systems. Besides, the test methods to examine linearity, such as IIP3, are also developed for narrow bandwidth systems. It is necessary to develop a new analysis method for wideband systems in the future.

A 33 to 60 GHz single-pole double-throw switch is reported in Chapter 5. The insertion loss is less than 4 dB within the bandwidth and the best isolation is -32.6dB at 41 GHz. It has 27 GHz bandwidth centered at 46.5 GHz for a flat insertion loss. The measured result is a little different from the simulated. The measured bandwidth is from 33 to 55 GHz. The bandwidth reduces to 22 GHz and the center frequency is down to 44 GHz. The measured data dropped fast beyond 50 GHz resulting from the un-precise device model which is given by the foundry. Besides, the inaccurate calibration also affects seriously.

Because the circuits are operated at high frequency, the parasitic effects are very significant and the EM simulations should be considered completely. The input/output pads, transmission lines, passive and active devices should be totally included to guarantee the precision of the circuit. Since the design of the wideband switches utilizes the concept of the maximally flat filters, the distance between each

components are fixed. As for the UWB LNA, the distance between two components should be as short as possible in order to reduce the parasitics. The considerations of the layout for these circuits are different. The most important is that the input and output ports should be allocated at first to simplify the measurement setup, especially for the totally on-wafer probing tests. If the locations of ports are not proper, it will lead to increase the difficulty for measurements.

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