Organization of the Thesis

In Chapter 2, we present the process flow utilizing double patterning technique for the fabrication of the NMOS devices with channel length down to 100 nm. We also present the characterization methods and measurement setups in this chapter.

In Chapter 3, characteristics of the fabricated devices are presented and discussed.

Special focus is paid on the effects of asymmetric source/drain halo structure on devices’ short-channel behaviors, hot-carrier reliability and low-frequency noise.

Finally, important conclusions generated from our experimental results, discussion and analysis are summarized in Chapter 4.

Chapter 2

Device Fabrication and Measurement Setup

2.1 Double Patterning Technique

A double patterning (DP) technique using twice I-line lithographic process and subsequent etching step has been developed and demonstrated to achieve 100 nm structure in our study. The two lithographic steps were performed with two different masks. Design of the two masks is shown in Fig. 2.1. The function of G1 mask is to protect the right side of active region to be covered with poly-Si during the subsequent (first) etching process, while the G2 mask protects the left side of the active region and covers portion of poly-Si region remained after the first etching. The overlapped region of the two masks defines the gate length. Although the process is more complicated than conventional one mask process, fine resolution down to 100 nm or even finer can be achieved with the proposed method, far beyond the capability of conventional I-line lithographic technique.

Figure 2.2 shows the in-line SEM images of a poly-Si line pattern formed with the above approach. In this thesis, Lmask represents the designed length on the mask, and Lgate is the practical value measured with In-line SEM. In Fig. 2.2, Lmask and Lgate are 100 and 93 nm, respectively. Figure 2.3 shows the profile of an etched poly-Si line with the focused ion beam (FIB) SEM. In this case Lmask and Lgate are 100 and 118 nm, respectively. The above results indicate that variation in the dimension of the gate patterns exists. In order to investigate the phenomenon we check the dimension of line patterns of different dies distributed on a wafer with the In-line SEM. Figure 2.4 shows the results of line patterns with Lmask of 100 nm measured from four dies located at corners of a wafer and the measured dimension

ranges from 91 to 124 nm. The measured results are shown in Fig. 2.5 to check the controllability of critical dimension (CD). The fluctuation of gate length is small as length is larger than 0.3 μm. The results indicate the double patterning technique is feasible to print lines with patterns down to 100 nm, far beyond the resolution limit (~350 nm) of single patterning technique with I-line stepper. However, the fluctuation in the CD of the fine patterns indicates the resolution of this method is mainly limited by the overlay of the stepper. According to the manual provided by the NDL, the overlay accuracy is about 45 nm. Nonetheless, the DP technique actually exhibits tighter CD control than the conventional single patterning one. This merit can be understood with the results shown in Fig. 2.6, in which the variation of CD for DP patterns with Lmask of 100 nm and patterns formed with conventional way with Lmask

of 350 nm are compared. These results confirm the feasibility of the proposed DP technique for fabrication of devices with much reduced feature size.

Actually we’ve also designed patterns with Lmask smaller than 80 nm, but we found the results are erratic and difficult to reproduce line patterns with tight dimension distribution. In this thesis we thus focus on fabricating devices with channel length equal or larger than 100 nm. Moreover, with the DP technique, effects of asymmetric halo on device characteristics can be studied.

2.2 Device Fabrication and Process Flow

Figure 2.7 illustrates the fabrication flow of NMOSFETs with basic process steps carried out in our experiment. All the devices were fabricated on 6-inch p-type (100) Si wafers with resistivity of 15~25 Ω-cm and wafer thickness of 655 ~ 695 μm. First the p well was formed by BF2+

implantation at 70 keV with dose of 1×10¹³ cm^-2 and the well drive-in was carried out at 1100 ℃ for 12 hours. Next, a standard local

oxidation of silicon (LOCOS) process with channel stop implant (by BF2+

implantation at 120 keV with dose of 4×10¹³ cm^-2) was used for device isolation.

Threshold voltage adjustment and anti-punch through implantation were done by implanting 40 keV BF2+

and 35 keV B⁺, respectively. When the LOCOS process was done, 3 nm-thick thermal gate oxide grown in N₂O ambient and a 150 nm in situ n⁺ doped poly-Si layer deposited by low-pressure chemical vapor deposition (LPCVD) were formed on wafer surface.

Details about the halo and source/drain (S/D) implantation conditions are shown in Table 2.1. The other implantation conditions used in the fabrication were shown in Table 2.2. For one set of devices, an optional halo implant was done after the gate-1 process, as shown in Fig. 2.7(c) (denoted as S-halo in Table 2.1). In this case the halo is located at the sources side. In contrast, D-halo device listed in Table 2.1 having a drain-side halo received an optional halo implant which was done after gate-2 process as shown in Fig. 2.7(d). It should be noted in this case that, during the halo implant, the PR remained in place to block the source side. We’ve also fabricated devices with symmetric halo, denoted as S/D-halo in Table 2.1, which have the halo formed by stripping off the PR after gate-2 process. The control or Control samples skipped the halo implants mentioned above. For all splits of devices, the S/D extension regions were formed by As⁺ implantation at 10 keV with dose of 1×10¹⁵ cm^-2 (Fig. 2.7(e)).

Afterwards, a 100 nm TEOS spacer was formed, followed by the formation of S/D regions by As⁺ implantation at 15 keV with dose of 5×10¹⁵ cm^-2 (Fig. 2.7(f)). Then the substrate contact region was patterned through lithography and etching processes, followed by a BF2+

implantation at 40 keV with dose of 5×10¹⁵ cm^-2. Rapid thermal anneal (RTA) was subsequently carried out in a nitrogen ambient at 1000 C for 10 second to activate dopants in the gate, S/D, and substrate contact regions. After a

standard procedure to form the surface passivation (Fig. 2.7(g)) and contact pads (Fig.

2.7(h)), the wafers received a forming gas anneal performed at 400 C for 30 min.

Cross-sectional views of the four splits of test structures are shown in Fig. 2.8.

2.3 Measurement Setup

2.3.1 Electrical Measurement Setup

Electrical measurements of all devices were evaluated by an HP4156A precision semiconductor parameter analyzer and an HP4284 LCR meter. The measurement systems were applied separately to gauge the current-voltage (I-V) and capacitance-voltage (C-V) characteristics. Temperature-regulated hot chucks were used to maintain the measurement temperature at 25 C

2.3.2 Hot Carrier Reliability Measurement Setup

In our study, we’ve performed the hot carrier reliability test to evaluate the performance of the asymmetric halo structures. Hot carrier generation is a strong function of the biasing voltage and the channel length of devices. To ensure small fluctuation in device characteristics so that the validity of test results was not seriously affected, we choose the devices with channel length of 0.14 μm for the testing which were stressed with the drain voltage set at a moderate positive voltage and the gate voltage at which maximum absolute value of substrate current (I_sub) occurred. This was determined by first measuring the Isub -VG characteristics with moderate positive drain voltage. To monitor the hot-carrier induced degradation, both the ID-VG characteristics at VDS = 0.05 V (linear region) and charge pumping current were measured before and after the stress. The degradations in terms of threshold voltage shift (V_th), generation of interface trap density (N_it) were recorded and

analyzed in the accelerated stress test.

2.3.3 Charge Pumping Measurement

For better understanding the damage mechanism of hot-carrier stress, it is desirable to plot the distribution of both generated interface states and trapped charges.

Charge pumping measurement is widely used to characterize the interface state density in MOSFET devices [21]. This type of measurement is very effective because it allows the exclusion of gate leakage contribution to the calculated interface state densities presented in thin gate oxides and at lower frequencies [22-23]. Therefore, to accurately analyze interface state densities or bulk traps in the dielectrics from charge pumping measurement results, we need to pay close attention to the extra leakage current issue. The basic charge pumping measurement includes the measurement of the substrate current while a series of voltage pulses with fixed amplitude, rise time, fall time, frequency, and duty cycle is being applied to the gate of the transistor (Figure 2.9), with source and drain connected to a small reverse bias, and substrate connected to ground. Three conventional types of the voltage pulse train applied to the gate electrode are depicted in Fig. 2.10, namely, (a) fixed amplitude sweep, (b) fixed base sweep, and (c) fixed peak sweep. In this thesis, “fixed amplitude sweep” is used to calculate interface trap density, and “fixed base sweep” is used to analyze the lateral distribution of interface trap, respectively. Square-wave waveforms (f = 1 MHz) were applied to the gate, and the base voltage was varied while keeping the pulse amplitude at 1.5 V to modulate the surface condition from inversion to accumulation.

An MOSFET with gate area of AG gives the charge pumping current (Icp) as [24]:

I_cp qA fN_{G it} , (2.1) which the interface trap density (N_it) could be calculated as I_cp is measured. The

lateral distribution of generated interface states after the hot-carrier stress was also

extracted and discussed in this work. This method is built up with the work of C.

Chen et al. [25], and the measurement setup is shown in Fig. 2.10. The measurement procedures are described below:

(1) Measure the Icp-Vh (Vh is the high level of the pulsed voltage train applied to the gate, see Fig. 2.10) curve on a virgin MOSFET from the drain junction (with the source junction floating), thereby establishing the Vh versus Vth(x) relationship near the junction of interest [26].

(2) Record the Icp-Vh characteristics after hot-carrier stress.

(3) The hot-carrier-induced interface state distribution, Nit(x), is obtained from the difference between the I_cp-V_h curve before and after hot carrier stress.

Table 2.1 Split condition of asymmetric halo structure with double patterning process.

Table 2.2 Other implantation conditions used in the NMOS fabrication.

Halo^{(BF2/5e12cm-2/40}

keV/Tilt=45°/Twist=27°)

Extension S/D Deep S/D

Control: Without halo(control)

As⁺ / 1e15 / 10 keV As⁺ / 5e15 cm^-2 / 20 keV S/D-halo: S/D halo

D-halo: Drain halo S-halo: Source halo

Conditions Ion Dose / Energy

P-well BF2 1e13 cm^-2 / 70 keV

Channel Stop BF2 4e13 cm^-2/ 120 keV

V_th BF2 1e13 cm^-2/ 40 keV

APT B⁺ 5e12 cm^-2 / 35 keV

Substrate BF2 5e12 cm^-2/ 40 keV

Chapter 3

Results and Discussion

3.1 Electrical Characteristics of Asymmetric Halo Devices

3.1.1 Electrical Characteristics of Symmetric NMOSFETs

Above all, this work is to discuss the impacts of halo formation and its location on the performance of NMOSFETs. For the readers’ convenience, we name all splits of test samples as follows: Control represents the control split without halo, S/D-halo represents the control split with symmetric halo, D-halo represents the control split with the drain-side halo, and S-halo represents as control split with the source-side halo. Figure 2.8 shows all splits with different structure.

Figure 3.1(a) and Figure 3.1(b) show the transfer characteristics of Control devices with various channel length under different drain bias. As the channel length scales down to 0.1 μm, the flow of bulk punchthrough current becomes obvious and results in degradation of subthreshold characteristics in Control samples. Here we used charging sharing model (Yau, 1974) to illustrate the sharing of the charges in the channel depletion region with the source and drain (S/D) junctions, as shown in Fig.

3.2. In a long channel device, drain and source are so distant that their depletion regions have negligible effects on the potential distribution in the channel. As the channel is sufficiently short and comparable to the width of channel depletion region along the horizontal direction, the portion of charge sharing with S/D junctions becomes significant, resulting in Vth lowering. When a high drain bias is applied to the short-channel device, the depletion region of the drain junction further penetrates into the channel. This may lead to lowering of potential barrier height at channel surface, as shown in Fig. 3.3 and Fig. 3.4. It indicates that the gate controllability weakens

when the gate length becomes smaller.

Figure 3.5 shows and compares the subthrehold characteristics for Control and S/D-halo (with symmetrical halo) devices with channel length of 0.1 μm. As can be seen in the figure, the implementation of halo steepens the subthreshold characteristics while the off-state leakage current is reduced by three orders in magnitude due to improved subthreshold swing (SS) and increased threshold voltage (V_th). We can use the illustrations in Fig. 3.4 and Fig. 3.6 to explain the observed difference revealed in Fig. 3.5. The implementation of halo tends to increase the substrate doping concentration therein and thus reduces the depletion width at channel edges, as shown Fig. 3.6. Furthermore, the lowering in surface potential barrier height with a higher drain voltage is also relieved.

The measured threshold voltages at VDS = 0.05 V as a function of channel length for the two types of devices are shown in Fig. 3.7. The threshold voltage is defined as the gate voltage at drain current of (W/L)．10nA, where L is the channel length and W is the channel width. We note that the two types of devices depict reverse-short-channel-effect (RSCE) which is much severe for S/D-halo. This is reasonable since halo increases doping distribution near the edge of the channel and results in a higher Vth locally. Figure 3.8 shows the drain-induced-barrier-lowering (DIBL) effect. It is clearly seen that the halo structure reduce DIBL significantly.

Subthrehold swing is another guide for evaluating the short-channel effects. The results are shown in Fig 3.9. It appears that devices with halo indeed improve short channel effects. Nevertheless, the halo may degrade the drain current. Figure 3.10 shows that the on-current of the halo devices is much smaller than devices without halo. In the figure it also appears that off-current distribution in Control is wider than S/D-halo, indicating that the halo can help suppress the fluctuation in device characteristics.

3.1.2 Electrical Characteristics of NMOSFETs with Asymmetrical

As demonstrated in previous section, halo implantation effectively improves the SCEs in MOSFETs. However, it has some drawbacks, such as the drain-substrate coupling, the degradation of driving current and enhanced RSCE. Recently some new MOSFET structures were proposed, such as single halo [27-29], which reduced the problems by eliminating the halo implantation. In order to explain the enhanced threshold voltage variation with the halo implant, a schematic illustration is shown in Fig. 3.11, in which the channel is divided into three regions, including the two halo implant regions near the drain and source with threshold voltage value of Vt1 in the source junction and V_t3 in the drain junction, respectively. The rest of the channel without halo is with Vt2, which is smaller than that in the halo region.

To examine the effect of asymmetrical halo structure, we further characterize the D-halo and S-halo devices fabricated in this study. Threshold voltage roll-off characteristics of all splits of devices are shown in Fig. 3.12. We note that, as channel length scales down to 0.1 μm, threshold voltage of the D-halo device (drain-side- halo) is slightly larger than S-halo device (source-side halo), but smaller than that of S/D-halo device (symmetrical halo). Such trend is reasonable when considering the charge sharing model shown in Fig. 3.2. Note in Fig. 3.12, the applied V_DS is small (0.05 V) but not zero, thus the width of depletion region at drain junction is slightly thicker than that at source junction, thus the Vth increase for D-halo is also more significant.

Figure 3.13 and Fig. 3.14 show the DIBL effect and SS as a function of channel length for different splits. From the figures we can see that the S/D-halo devices exhibit the best performance in suppressing the SCEs, although the D-halo devices show comparable effectiveness. Since the SCEs are closely related to the penetration

Halo

of electric field from the edge, especially that originating from the drain with a non-zero drain bias, the D-halo split with drain halo should have better immunity than S-halo devices. We use Fig. 3.15 and Fig. 3.16 to illustrate the depletion width of drain junction. The D-halo has a smaller drain depletion width, thus a smaller charge sharing and less field penetration from the drain as channel length is reduced, resulting in less Vth roll-off and DIBL.

Figure 3.17 shows that the on-current of all splits. Asymmetric halo devices show better on-current than symmetric halo device. On the other hand, symmetric halo device shows reduced off-current as shown in Fig. 3.18. However, this is mainly caused by the severe RSCE (Fig. 3.7) which increases the threshold voltage significantly.

3.2 Hot Carrier Degradation of Asymmetric Halo Devices

3.2.1 Hot Carrier Stress

Mechanisms of hot-carrier induced degradation in MOS devices are strongly related to the impact ionization in the high electric-field region near the drain junction [30-31]. For NMOSFET devices, these generated electrons and holes during impact ionization process are separately collected by the drain and the substrate terminals.

Hence both the substrate current (Isub) and the impact ionization rate (Isub/ID) have been widely used as indexes of the amount of electron-hole pairs generated by impact ionization. The substrate current versus gate voltage for all splits of devices are shown in Fig. 3.19(a). It can be seen that the substrate current of the S/D-halo split is larger than that of other splits. Figure 3.19(b) shows the impact ionization rate (I_sub/I_D) of the four types of devices. It is apparent that the higher impact ionization rate is closely related to the implementation of halo structures inside the substrate. This result shows

clearly that the halo implantation greatly affects the generation of channel hot electrons and the associated impact ionization process. Among all devices, the S/D-halo split exhibits the highest Isub which is attributed to the increase in peak lateral electric field under the gate edge of drain junction in the devices [32-33]. On the other hand, the impact ionization rate of the Control and the S-halo devices are much lower than that of the S/D-halo device due to lack of drain halo implantation.

From the above discussion, it is inferred that the devices with drain halo implantation would show aggravated hot-carrier degradation. This postulation can be confirmed by measuring the subthreshold characteristics and transconductance of devices before and after 3000 second hot-electron stressing, and the results are shown in Figs. 3.20(a) ~ (d). The ID-VG characteristics were measured at VDS = 0.05 V with channel width/length = 10 m/0.14 m. As expected, the degradation is the worst in the S/D-halo sample among all splits, in terms of transconductance reduction and threshold shift increase.

Figures 3.21(a) ~ (c) show threshold voltage shift (V_th), increased interface state density (ΔNit), and degraded peak transconductance (Gm), respectively, as a function of stress time for all splits stressed at V_DS = 3 V and V_GS at maximum substrate current. All devices are with channel W/L = 10/0.14 m. As mentioned above, the devices with drain halo implantation depict aggravated degradation in terms of larger shift in these parameters. We suspect that the peak lateral electric field in the channel [34] is the primary culprits for the aggravated hot carrier degradation.

Note that, although the drain halo implantation may significantly worsen the degradation, the degradation of S/D-halo sample is higher than D-halo sample even though the drain halo dose is the same for both splits. This can probably explained by

Note that, although the drain halo implantation may significantly worsen the degradation, the degradation of S/D-halo sample is higher than D-halo sample even though the drain halo dose is the same for both splits. This can probably explained by