Chapter 1 Introduction
1.3 Organization
In chapter 2, the basic operations of conventional 6T, the previous 10T Schmitt Trigger sub-threshold SRAM cells and proposed 8T Schmitt Trigger sub-threshold SRAM cells are described. Chapter 3 investigates the cell RSNM, WSNM, HSNM and with considering self-heating and temperature dependence, and cell leakage in sub-threshold region. The cell layouts, areas, and cell AC performance (such as cell Read access time, cell Write time (Time-to-Write), Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage, and temperatures dependence) are assessed based on scaled ground rules from 32 nm node in Chapter 4. In Chapter 5, describe the methodologies of LER (Line Edge Roughness), and then 3D mixed-mode Monte Carlo simulations are performed to
evaluate the impacts of local random variations, notably the Gate LER and Fin LER on FinFET SRAM stability. The combined effects with main process variations (Leff
and Wfin(Tsi,)) are then strictly examined for more robustness of cell stability. For overall robustness of cell stability, the sensitivity of process (Leff, EOT, Wfin(Tsi,), and Hfin) is also discussed. In the end of chapter 5, introduce another probability of local random variation – work function variability (WFV). The conclusion of the paper is given in Chapter 6.
0.0 0.2 0.4 0.6 0.8 1.0 0.0
0.2 0.4 0.6 0.8 1.0
V L (V )
VR(V)
Fig. 1.1. Schematic of conventional 6T (6T).
Fig. 1.2. The stability of 6T deteriorates significantly.
WL
BL BR
VCS
PL PR
NL NR
AXL AXR
VL
VR
Fig. 1.3. Schematic of various bulk CMOS sub-threshold cells: (a) 10T [4], (b) high-density 10T [5], (c) fully differential 10T [6].
(a)
(b)
(c)
Fig. 1.4. Schematic of various FinFET cells: (a) Schmitt Trigger 10T (ST1) [3], and (b) Schmitt Trigger 10T (ST2) [9].
BL VCS
WL
BL BR
AXL
AXR
PL PR
NL NR
VCS
VL VR
WWL
BL BR
AXL
AXR
PL PR
NL NR
VCS
VL VR
R/WWL
Fig. 1.5. Schematic of various independently-controlled-gate FinFET cells: (a) Ying-Yang feedback 6T [10], (b) improved Ying-Yang feedback 6T [11], (c) double word-line 6T [12], and (d) asymmetrical 6T [13].
(a) (b)
(c) (d)
Fig. 1.6. Schematic of proposed Schmitt Trigger based Independently-Controlled Gate FinFET cells: (a) IG_ST1, (b) IG_ST2, and (c) IG_ST3.
WWL BR
Chapter 2
Schmitt Trigger Based FinFET SRAMs
2.1 Introduction
With aggressive scaling of transistor dimensions, the density of transistor in integration circuit is increased more and more today. So that the power consumption will be a significant concern especially in SRAM design. Fig 2.1 shows the effective way to reduce the power consumption by reducing the VCS which can reduce active power quadratically and static leakage power linearly [16]. Therefore, circuit operate in low voltage is important for today SRAM design. However, as supply voltage decreased into sub-threshold region, the sensitivity/stability is severe to process and local random variation [17]. To overcome this problem, some different SRAM cells have been proposed, though none of them have a built-in feedback mechanism to improve the stability under the process variation.
In previous works [3, 9], ST1 and ST2 have been proposed to improve the stability under the process variation. However, the bigger cell area would be another disadvantage factor in SRAM design. In this work, our initial idea is to remain the advantage of Schmitt Trigger action, and also reduces the cell area. Based on this idea, we use the capability of independent gate control in double-gate FinFET devices to create three new cells, thus successfully reduce the cell area. In the following section, we will basically introduce the operation of conventional 6T, ST1 and ST2 cells, and clearly introduce the operation (Read, Write, and Hold mode) of our new cells.
2.2 Conventional 6T SRAM
Fig. 1.1(a) shows conventional 6T cell structure in common SRAM design. This cell has two complementary bit-lines which are used to sensing data or writing data.
There is one word-line which controls access transistors (AXR and AXL) to access the cell for Read or Write operation. In Hold mode, The cell consists of a pair of cross-coupled inverters to store the data.
For Read operation, bit-lines are precharged to VDD initially and word-line turns on. Thus, one of the bit-lines will be discharged by pull-down transistor (NL or NR).
For an example, assume VL=0 VR=VCS, BL will be discharged by AXL and NL from VDD to 0. In order to accelerate the discharge velocity, sense amplifier (SA) is also one of the important part in SRAM design, which can detect the small differential voltage and transforms into full swing quickly. For Write operation, in order to Write 0 or Write 1, there is one of the bit-lines will first be pulled down by write driver, and then word-line turns on. Thus, data of storage node will be flipped. For an example, assume VL=0, VR=VCS, BL=VDD, and BR=0, VR is going to be pulled to low, and VL will rise to high. Fig. 2.2 shows the schematic of Read/Write operating behavior.
2.3 Previous 10T Schmitt Trigger Cells
In previous works [3, 8], ST1 and ST2 use Schmitt Trigger characteristics to enhance RSNM in low voltage operation. For ST1 (Fig. 1.4(a)), the feedback mechanism from NFR (NFL) that conditions the intermediate stacking node VNR (VNL) is adaptively enabled according to the direction of input transition (1 to 0, or 0
to 1). During Read operation (assume VL=0 VR=VCS), the voltage of VL would rise to Vread (Fig. 2.3(a)) due to the voltage divider effect between AXL and pull-down transistors (NL1-NL2). If Vread is higher than the switching threshold Vtrip (Fig. 2.3(a)) of the opposite cell inverter (PR-NR1-NR2), the data in cell storage nodes would be flipped, thus causing Read failure. With the Schmitt Trigger feedback mechanism, the Vtrip of the inverter (PR-NR1-NR2) is increased due to (1) higher VNR node voltage, which is conditioned to one VT below VR (= VCS) by the feedback transistor NFR, and (2) higher VT of NR1 owing to its reverse body-to-source bias. As such, the RSNM improves and the stored data in VL and VR is preserved. The detailed Voltage Transfer Characteristics (VTC) is shown in Fig. 2.3 (c), where the improved RSNM due to higher Vtrip can be seen. During Write operation (again assume VL=0 VR=VCS), the feedback transistor NFL turns off. Due to series combination of pull-down transistors NL1 and NL2, the Vtrip of the inverter (PL-NL1-NL2) is raised to higher voltage, resulting in better Write margin and Write-ability.
The ST2 cell uses AXR2 (AXL2) to adaptively control cell inverter switching threshold. The gates of the feedback transistors AXR2 (AXL2) are connected to word-line to provide a firmer/stronger intermediate node conditioning action than that in ST1 where the gates of NFL (NFR) are connected to cell storage nodes. Moreover, during Write operation, AXR2 (AXL2) provides extra path to discharge the cell internal nodes to improve the Write margin and performance. Therefore, both RSNM and Write-ability are further enhanced compared with ST1.
2.4 Proposed 8T Schmitt Trigger Cells
Due to the flexibility of Independently-controlled-Gate (IG) operation in FinFET structure, the role of the Schmitt Trigger feedback transistor could be realized from the existing transistor NR1 (NL1). By splitting the front- and back-gate of NR1 (NL1), one can use the front-gate as the stacking device, and the back-gate as the intermediate node conditioning device to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area.
Three novel SRAM cell structures are proposed in this work. IG_ST1 (Fig.
1.6(a)) forms Schmitt Trigger feedback path by connecting the back-gate of NR1 (NL1) to cell storage node VR (VL). During Read operation (assume VL=0 VR=VCS), the feedback mechanism is enabled with the node voltage VNR conditioned to one diode drop (VT) below VR by the back-gate of NR1, thus increasing Vtrip of the cell inverter (PR-NR1-NR2) and improving the RSNM. Notice that as VL rises and VR falls, the feedback (intermediate node conditioning) mechanism becomes weaker and the switching slope (steepness) of IG_ST1 cell would degrade. Notice also that split-gate configuration is used for the access pass-transistor AXL (AXR), so only one gate is enabled during Read to reduce Read disturb, while both gates are enabled during Write to improve Write-ability and performance. During Write operation (assume VL=0 VR=VCS), due to reduced NL1 strength with its back-gate connected to VL (= 0), and the series NL1-NL2 pull-down configuration, the trip voltage of the left cell inverter (PL-NL1-NL2) is raised, thus further improving the Write-ability.
In IG_ST2 (Fig. 1.6(b)), the back-gates of NR1 (NL1) and AXR (AXL) are connected to the R/WWL. The connection of the back-gates of NR1 (NL1) to R/WWL provides a firmer/stronger intermediate node conditioning action, and a steeper switching transition (since the back-gate of NR1 is always “High” during
Read) than IG_ST1. Furthermore, during Write operation (VL=0 VR=VCS), due to stronger NL1 with its back-gate always at “High”, its Write-ability is slightly degraded with respect to IG_ST1 cell.
In IG_ST3 cell (Fig. 1.6(c)), the back-gates of NR1 (NL1) are connected to VCS. Therefore, the cell would preserve the Schmitt Trigger feedback mechanism even when the R/WWL and WWL are turned off (i.e. Hold mode). In Read and Write mode, IG_ST3 cell has the same Schmitt Trigger feedback mechanism as IG_ST2 cell.
Hence, IG_ST3 would have better HSNM, and the same RSNM and WSNM compared with IG_ST2 cell.
Fig. 2.4(a) shows the FinFET device structure studied in this paper and Fig. 2.4(b) shows the tied-gate and independently-controlled-gate configurations [10]. Our analyses are based on FinFET device with Na=1×1017cm-3, Leff=25nm, Wfin(Tsi,)=7nm, Hfin=20nm and EOT=0.65nm, consistent with the ITRS Roadmap projection. The threshold voltage of the devices are VTN ~ 0.43 V and VTP ~ 0.45 V. The Framework of following TCAD 3D mixed-mode simulations including DC (SNM) and AC (Read and Write time) metrics are illustrated in Fig. 2.5, using individual transistors for various SRAM cells, and our simulations are based on drift-diffusion equations.
2.5 Summary
In this chapter, we introduce basic conventional 6T Read/Write operation, and then introduce the characteristic of Schmitt Trigger Based 10T cells (ST1 and ST2).
The main advantage of ST1 is increasing Read stability and has built-in process
variation tolerance. The improved version ST2 gain lower Read disturb and better Write margin at the cost of two word-lines structure.
In this work, we reduced two transistors to create FinFET Schmitt Trigger cells.
IG_ST1 use storage node connecting to back-gate of feedback transistor for Schmitt Trigger action, IG_ST2 use R/WWL connecting to back-gate of feedback transistor for Schmitt Trigger action, and IG_ST3 use supply voltage connecting to back-gate of feedback transistor for Schmitt Trigger action. It is detailed to explain the operation of three proposed new cells, including Read, Write and Hold mode.
Fig. 2.1. Active, static, and total energy consumption versus VDD [16].
Fig. 2.2. Schematic of 6T (a) Read, and (b) Write operation.
Fig. 2.3. Voltage transfer characteristic curves used to calculate SNM: (a) Read and Hold mode, (b) Write mode, and (c) ST1 in Read mode.
RSNM
RV L (V )
VR(V) RSNM
LVtrip
HSNM
RHSNM
LV read
WSNM
LWSNM
RV L (V )
VR(V)
RSNM
RRSNM
LV L (V )
VR(V)
(a)
(b)
(c)
G S/D
S/D Insulator
BOX L eff
W fin (T si ) H fin
Fig. 2.4. (a) FinFET device structure, and (b) tied-gate and independently-controlled-gate configurations [18].
(a)
(b)
Fig. 2.5. Framework of TCAD 3D mixed-mode simulations.
Chapter 3
SNM and Standby Leakage Current Analysis
3.1 Introduction
Static Noise Margin (SNM) is a common criterion to investigate SRAM cell stability in DC mode, which is including Read, Write, and Hold mode. The RSNM is defined as the length of a side of maximum square that can fit inside the butterfly curves in Read mode [19], and the minimum of RSNML and RSNMR is chosen as the cell RSNM (Fig. 2.3(a)). The HSNM is defined similar to RSNM with the cell in Standby (Hold) mode. The WSNM is defined as the minimum square spanning between the curves in Write mode (Fig. 2.3(b)), and the smaller of WSNML and WSNMR is chosen as the cell WSNM. Due to the asymmetrical Voltage Transfer Curves (VTC) for ST1 cell (the direction of input transition (1 to 0, or 0 to 1)), the corresponding RSNM is as shown in Fig. 2.3(c). In this chapter we will comprehensively compare RSNM, WSNM, and HSNM with these sub-threshold SRAM cells.
Previous section has mentioned that static power consumption would be a critical concern when SRAM operates in sub-threshold region. In [3], this paper indicated that as the same Read failure probability, ST1 cell can save 18% static leakage power than 6T cell. But under this condition, ST1 operates at 175 mV lower supply voltage than 6T cell. In this chapter, for the fair comparison, we set the same supply voltage (VCS=0.4V) to compare all the cells’ static leakage current.
3.2 Comparison of Read, Write and Hold SNM
In Fig. 3.1 (a), the normalized nominal RSNM of different cells are compared in sub-threshold region (VCS = 0.4V). With the help of feedback mechanism, Schmitt Trigger based cells show significantly better nominal RSNM (35% - 81%) than the conventional 6T cell. In particular, IG_ST2 and IG_ST3 have the most significant improvement in nominal RSNM (~81%) due to their steeper switching characteristics.
In Write mode (Fig. 3.1(b)), Schmitt Trigger based cells also show better nominal WSNM (1% to 33%). The improvement is most significant for ST2 cell due to its two parallel discharging paths for cell internal nodes and tied-gate pass-transistor configuration. In Hold mode (Fig. 3.1(c)), IG_ST1 and IG_ST2 have slightly lower nominal HSNM due to the split-gate configuration of NL1 (NR1) which slightly degrades the switching slope (steepness). Notice that IG_ST1 maintains the feedback mechanism even in Hold mode, as the intermediate node VNL (or VNR) is still conditioned by the back-gate of NL1 (or NR1) to one VT drop below the “High” cell storage node. Also the VT of the front-gate of NL1 (or NR1) will be lower due to gate-to-gate coupling. The switching transition also tends to be soft as the feedback mechanism weakens and eventual diminishes with the switching transition.
For IG_ST2 in Hold mode, the back-gates of NL1 (and NR1) are at “Low”, hence there is no feedback mechanism. The VT of the front-gates of NL1 and NR1 will be a little bit higher due to gate-to-gate coupling, thus Vtrip tends to be a little higher. The HSNM, however, does not constitute a limitation on SRAM stability, while RSNM does. IG_ST3 exhibits HSNM comparable to (1% better) 6T cell since it preserves the Schmitt Trigger feedback mechanism in Hold mode. The stability of the
cells operating at ultra-low-voltage is assessed in Fig. 3.2. It can be seen that RSNM is most critical for the supply voltage range from 0.4V down to 0.15V. Furthermore, the improvements of RSNM of the proposed cells over 6T cell become more significant as the supply voltage decreases. For IG_ST2 and IG_ST3 cell, the improvement increases from 81% to 110% as VCS scales from 0.4V to 0.15V.
Notice that during Write operation, both R/WWL and WWL are turned on, so both the front- and back-gate of the access pass-transistor AXL (AXR) are enabled. As such, the half-select disturb along the selected WL is more serious than the half-select disturb during Read operation. Notice also that other sub-threshold SRAM cells, like those in [4, 5], and previously reported 10T Schmitt Trigger sub-threshold SRAM cells [3, 9] have similar Write half-select disturb constraint. Therefore, non-bit-interleaving architecture or Byte Writing architecture should be used to best exploit the improved RSNM of these sub-threshold SRAM cells.
3.3 Self-Heating and Temperature Dependence on Sub-threshold SRAM Stability
Compared with bulk device, due to lower thermal conductivity (κ) in thin-film silicon layer on insulator devices (PDSOI, FDSOI, and FinFET), these devices have self-heating problem [20]. With the calibrated thermal conductivity data [21], thermal conductivity (κ) of thin-film is 15 W m-1K-1. Fig. 3.3 shows device temperature versus various VDD. As can be seen, in sub-threshold region (VDD=0.4V), device temperature keeps as ambient temperature. Therefore, it seems that self-heating can negligible in sub-threshold region. The lattice temperature
distribution of our simulation devices at VDD=0.4V and VDD=1V is shown in Fig. 3.4.
Fig. 3.5 shows RSNM comparison of various cells at VDD=0.4V versus temperature. We accessed with and without self-heating for RSNM comparison.
Because cell operates in sub-threshold region (VDD=0.4V), no matter considering self-heating or not, RSNM comparison of various cells are the same. It can be seen, RSNM of all cells slightly degrade ~10 mV as increasing temperature from 250K to 400K. This is because at 400K that sub-threshold swing is degraded [22] and operates in super-threshold region resulting higher Vread [23]. For an example, In Fig. 3.6, 6T butterfly curves of 250K and 400K are shown to explain this phenomenon.
3.4 Comparison of Standby Leakage Current
In sub-threshold region, static leakage power is a dominant source for power consumption. When SRAM operates in Standby mode, the schematic for leakage current path for 6T is shown in the Fig. 3.7. The conditions of cell storage nodes are VR=”Low” and VL=”High”.
Fig. 3.8 compares the Standby leakage current of different cells. The conditions of cell storage nodes are VR=”Low” and VL=”High”. Compared with 6T cell, Fig. 3.9 illustrates that ST1 and ST2 have extra leakage path through NFR and AXR2, and therefore exhibit 36% and 19% higher Standby leakage current, respectively. The proposed cells leakage path illustrate in Fig. 3.10. Without extra cell leakage path, IG_ST1 and IG_ST3 show slightly lower leakage (4%) compared with 6T cell.
Moreover, IG_ST2 cell, with the back-gate of the stacking transistor (NL1/NR1) off
in Standby, reduces up to 21% cell leakage current compared with 6T cell.
3.5 Summary
We have analyzed overall SRAM stability, including Read, Write, and Hold mode.
Schmitt Trigger based cells could significantly have better nominal RSNM (35% - 81%) than the conventional 6T cell. In particular, IG_ST2 and IG_ST3 have the most significant improvement in nominal RSNM (~81%). Write ability of Schmitt Trigger based cells are slightly improved due to stacked pulled-down NMOS transistors. In Standby mode, stability is more robust than Read mode. In particular, As VCS scales from 0.4V to 0.15V, for IG_ST2 and IG_ST3, the RSNM improvement increases from 81% to 110%.
With considering self-heating in FinFET devices, device temperature is not impacted by self-heating effect in sub-threshold region (VDD=0.4V). Furthermore, in SRAM level simulations, increasing temperature from 250K to 400K, RSNM is slightly degraded 10 mV for each cells.
In the second part, cell leakage analysis has been investigated. At VCS=0.4V, due to extra leakage path through feed-back transistors, ST1 and ST2 cells exhibit 36%
and 19% higher Standby leakage current, respectively. Our proposed cells can save 20% to 50% cell leakage current than previously reported ST1 and ST2 cells, because of the stacking transistors.
Fig. 3.1. Comparison of normalized nominal (a) RSNM, (b) WSNM, and (c) HSNM
Fig. 3.2. Comparison of nominal (a) RSNM, (b) WSNM, and (c) HSNM in ultra-low voltage operation.
0.15 0.20 0.25 0.30 0.35 0.40 30
0.15 0.20 0.25 0.30 0.35 0.40 50
0.15 0.20 0.25 0.30 0.35 0.40 50
0.4 0.5 0.6 0.7 0.8 0.9 1.0 300
350 400 450 500
D e v ic e T e m p e ra tu re (K )
V
DD(V)
Ambient Temperature=300K FinFET Average Temperature FinFET Maximum Temperature κ
κκ
κ=15 (W/mK)
Fig. 3.3. Impact of VDDon the device average and maximum temperature FinFET SOI device (ambient temperature is set to 300K).
Fig. 3.4. Temperature distribution in whole FinFET device at (a) VDD=0.4V, and (b) 1V respectively.
(a) (b)
250K 300K 350K 400K
Fig. 3.5. Impact of temperature on RSNM for various FinFET sub-threshold cells.
Fig. 3.6. Butterfly curves of 6T degrade at high temperature (400K) which is because of degradation of sub-threshold swing and higher Vread.
Fig. 3.7. Schematic of Standby leakage path for 6T.
Fig. 3.8. Comparison of cell Standby leakage current (at VCS = 0.4V) of various cells.
6T ST1 ST2 IG_ST1 IG_ST2 IG_ST3
0.0 0.5 1.0
1.5
Sub-threshold(VCS=0.4V)-4%
-21%
-4%
19%
Normalized Standby Leakage Current
36%
WL
BL BR
VCS
PL PR
NL NR
AXL VL AXR
VR
Fig. 3.9. Schematics of Standby leakage path for (a) ST1 and, (b) ST2.
Fig. 3.10. Schematics of Standby leakage path for (a) IG_ST1 , (b) IG_ST2, and (c)
Chapter 4
Cell Area and AC performance
4.1 Introduction
Area of SRAM is usually the biggest part in whole chip area today ~ 90% [24].
Schmitt Trigger based cells use adding extra transistors to gain better stability, but at the expense of increased area. Due to various cell structures, the layouts are in different way. In this chapter, we will illustrate one possible “thin cell” layout for various cells, and estimate the corresponding area overhead.
We have investigated various SRAM cells stability in DC mode. On the other hand, transient (AC) analysis is a need to show the timing information in Read and Write mode. In the following section, we can get a capacitive load onto each bit-line from estimated cell height and then evaluate Read time and Write time (Time-to-Write). In order to make sure successful Read in the worst SRAM bit-line pattern, the worst-case bit-line leakage current has been considered. In addition, increased leakage current caused by temperature also has been considered with
We have investigated various SRAM cells stability in DC mode. On the other hand, transient (AC) analysis is a need to show the timing information in Read and Write mode. In the following section, we can get a capacitive load onto each bit-line from estimated cell height and then evaluate Read time and Write time (Time-to-Write). In order to make sure successful Read in the worst SRAM bit-line pattern, the worst-case bit-line leakage current has been considered. In addition, increased leakage current caused by temperature also has been considered with