Chapter 1 Introduction
1.2 Organization
This dissertation includes six chapters.
In Chapter 1, the background and the motivation of this thesis are discussed.
In Chapter 2, we introduce the BSIM-based method for the Rsd extraction [20].
Using this method, Rsd can be well extracted in nano-scale strained devices. We have verified this method using samples with different process conditions and good agreement with experimental data has been obtained. This BSIM-based method is also verified by TCAD simulated current-voltage (IV) characteristics [21]. The extracted Rsd will be used in the following chapters for the extraction of carrier mobility.
In Chapter 3, by using the split-CV method [22], the channel mobility in the short channel devices can be extracted by calibrating the extracted Rsd values from Chapter 2, as a shown in Fig. 1.1. Then we assessed the impact of process-induced uniaxial strain on Coulomb mobility in short-channel nMOSFETs and pMOSFETs under various temperatures [23,24]. We also utilized the four-point mechanical bending technique on both short and long channel devices in PMOSFETs. Our study indicates that the stress sensitivity of the Coulomb mobility shows strong temperature dependence due to the competition result of the stress sensitivity between bulk charge scattering and interface
Furthermore, the SR has higher strain dependence than the phonon scattering limited mobility (PH). Our experimental results confirm the previously reported results based on simulations [27,28] In addition, a wavefunction penetration perspective [29,30] is proposed to explain the possible physical origin of the uniaxial strain dependence of
SR.
In Chapter 5, we conduct an experimental assessment for the impact of process-induced uniaxial strain on the temperature dependency of carrier mobility in nanoscale pMOSFETs [31]. Furthermore, through cryogenic temperature measurement from Chapter 4, we investigate the impact of uniaxial strain on the temperature dependence of phonon-scattering limited mobility in nanoscale PMOSFETs [19]. The EEFF and temperature dependence of the extracted SR and PH will be discussed and benchmarked with published data [32,33]. Our study indicates that the strain sensitivity of hole mobility becomes less with increasing temperature and it is consistent with previous uniaxial mechanical bending result [18]. The temperature sensitivity of phonon mobility becomes higher when compressive strain is applied. It can be explained by the higher optical phonon energy induced by uniaxially-compressive strain. Our new findings also explain the higher temperature sensitivity of drain current presented in uniaxial strain PMOSFETs.
In Chapter 6, we summarize the key research results and the contribution of this thesis.
References
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[2] Scott E. Thompson, Guangyu Sun, Youn Sung Choi and Toshikazu Nishida,
“Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap,” IEEE Transactions on Electron Devices vol. 53(5), pp. 1010-1020, May 2006.
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Stierstorfer, L. Clevenger, S. Kim, J. Toomey, D. Sciacca, J. Li, W. Wille, L. Zhao, L.
Teo, T. Dyer, S. Fang, J. Yan, O. Kwon, D. Park, J. Holt, J. Han, V. Chan, J. Yuan, T.
Kebede, H. Lee, S. Kim, S. Lee, a. Vayshenker, Z. Yang, C. Tian, H. Ng, H. Shang, M.
Hierlemann, J. Ku, J. Sudijono, M. Ieong, “High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology,” Symp. VLSI Tech., pp. 16-17, June 2007.
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Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.
Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. E. Mansy, “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices vol.
51(11), pp. 1790-1797, November 2004.
[7] D. Esseni, H. Iwai, M. Saito, and B. Ricco, “Nonscaling of MOSFET‟s Linear Resistance in the Deep Submicrometer Regime,” IEEE Electron Device Letter, vol.
19(4), pp. 131-133, April 1998.
[8] Hans van Meer, Kirklen Henson, Jeong-Ho Lyu, Maarten Rosmeulen, Stefan Kubicek, Nadine Collaert, and Kristin De Meyer, "Limitations of Shift-and Ratio Based Leff Extraction Techniques for MOS Transistors with Halo or Pocket Implants,” IEEE Electron Device Letters, vol. 21(3), pp. 133-136, March 2000.
[9] Olivier Weber, and Shin-ichi Takagi, “New Findings on Coulomb Scattering Mobility in Strained-Si nFETs and its Physical Understanding,” Symp. VLSI Tech., pp.
130-131, June 2007.
[10] Hasan M. Nayfeh, Christopher W. Leitz, Arthur J. Pitera, Eugene A. Fitzgerald, Judy L. Hoyt, and Dimitri A. Antoniadis, “Influence of High Channel Doping on the Inversion Layer Electron Mobility in Strained Silicon n-MOSFETs,” IEEE Electron Device Letters, vol. 24(4), pp. 248-250, April 2003.
[11] F. Gamiz, J. B. Roldan, J.A. Lopez-Villanueva, and P. Cartujo, “Coulomb scattering in strained-silicon inversion layers on Si1-xGex substrates,” Appl. Phys. Lett., vol. 69(6), pp. 797-799, August 1996.
[12] Antoine Cros, Krunoslav Romanjek, Dominique Fleury, Samuel Harrison, Robin Cerutti, Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Romain Wacquez, Blandine Duriez, Romain Gwoziecki, Frederic Boeuf, Hugues Brut, Gerard Ghibaudo, Thomas Skotnicki, “Unexpected mobility degradation for very short devices: A new
Morphology,” Symp. VLSI Tech., pp. 134-135, June 2007.
[14] Y. Zhao, H. Matsumoto, T. Sato, S. Koyama, M. Takenaka and S. Takagi, “A Novel Characterization Scheme of Si/SiO2 Interface Roughness for Surface Roughness Scattering-Limited Mobilities of Electrons and Holes in Unstrained- and Strained-Si MOSFETs,” IEEE Transactions on Electron Devices, vol. 57(9), pp. 2057-2066, September 2010.
[15] F. Lime, F. Andrieu, J. Derix, G. Ghibaudo, F. Boeuf, and T. Skotnicki, “Low temperature characterization of effective mobility in uniaxially and biaxially strained nMOSFETs,” Solid-State Electronics, vol. 50(4), pp. 644-649, April 2006.
[16] Nobuyuki Sugii and Katsuyoshi Washio, “Low-Temperature Electrical Characteristics of Strained-Si MOSFETs,” Jpn. J. Appl. Phys., Part 1, vol. 42, pp.
1924-1927, 2003.
[17] M. N. Tsai, T. C. Chang, P. T. Liu, O. Cheng, and C. T. Huang, “Temperature Effects of n-MOSFET Devices with Uniaxial Mechanical Strains,” Electrochemical and Solid-State Letters, vol. 9(8), pp. 276-278, June 2006.
[18] Xiaodong Yang, Srivatsan Parthasarathy, Yongke Sun, Andrew Koehler, Toshikazu Nishida, and Scott E. Thompson, “Temperature dependence of enhanced hole mobility in uniaxial strained p-channel metal-oxide-semiconductor field-effect transistors and insight into the physical mechanisms,” Applied Physics Letter vol.
93(24), pp. 243503-243503-3, December 2008.
Extraction Method in Nanoscale MOSFETs,” Journal of The Electrochemical Society, vol. 156(1), H34-H38, 2009.
[22] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, “Improved Split C-V Method for Effective Mobility Extraction in sub-0.1-m Si MOSFETs,” IEEE Electron Device Letters, vol. 25(8), pp. 583-585, August 2004.
[23] William P.-N. Chen, P. Su, K. Goto, “Investigation of Coulomb Mobility in Nanoscale Strained PMOSFETs,” IEEE Transactions on Nanotechnology, vol. 7(5), pp.
538-543, September 2008.
[24] William P.-N. Chen, P. Su, K. Goto, “Impact of Process-Induced Strain on Coulomb Scattering Mobility in Short-Channel n-MOSFETs,” IEEE Electron Device Letters, vol. 29(7), pp. 468-470, July 2008.
[25] Kenneth Chain, Jian-Hui Huang, Jon Duster, Pin K Ko and Chenming Hu, “A MOSFET electron mobility model of wide temperature range (77-400K) for IC simulation,” Semiconductor Science Technology, vol. 12(4), pp. 355-358, 1997.
[26] William P.N. Chen, Jack J.-Y. Kuo, and Pin Su, “Experimental Investigation of Surface Roughness Limited Mobility in Uniaxial Strained pMOSFETs,” IEEE Electron Device Letters, in press.
[27] M. V. Fischetti, F. Gamiz, and W. Hansch, “On the enhanced electron mobility in strained-silicon inversion layers,” J. Appl. Phys., vol. 92(12), pp. 7320-7324, December 2002.
[28] S. T. Pantelides, L. Tsetseris, M. J. Beck, S. N. Rashkeev, G. Hadjisavvas, I. G.
[29] I. Polishchuk and C. Hu, “Electron Wavefunction Penetration into Gate Dielectric and Interface Scattering- An Alternative to Surface Roughness Scattering Model”, Symp.
VLSI Tech, pp. 51-52, June 2001.
[30] William P.N. Chen, Jack J.-Y. Kuo, Barney K-.Y. Lu and Pin Su, “Experimental Investigation and Modeling for Surface Roughness Limited Mobility in Strained pMOSFETs”, Extended Abstracts of the 2010International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, pp. 49-50, September 2010.
[31] William P.N. Chen, Jack J.-Y. Kuo, and Pin Su, “Impact of Process-Induced Uniaxial Strain on the Temperature Dependence of Carrier Mobility in Nanoscale pMOSFETs,” IEEE Electron Device Letters, vol. 31(5), pp. 414-416, May 2010.
[32] Shin-ichi Takagi, Akira Toriumi, Masao Iwasw, and Hiroyuki Tango, “On the Universality of Inversion Layer Mobility in Si MOSFET‟s: Part II – Effects of Surface Orientation,” IEEE Transactions on Electron Devices, vol. 41(12), pp. 2363-2368, December 1994.
[33] Kwyro Lee, Joo-Sun Choi, Sang-Pil Sim and Choong-Ki Kim, “Physical Understanding of Low-Field Carrier Mobility in Silicon MOSFET Inversion Layer,”
IEEE Transactions on Electron Devices, vol. 38(8), pp.1905-1912, August 1991.
CV measurement with Covcalibration
Id-VG measurement
Rsd& ideal drain current Inversion charge &
Rsd& ideal drain current Inversion charge &
Figure 1.1. The flowchart of the short channel mobility extraction.
Chapter 2
A New Series Resistance Extraction Method for Nanoscale MOSFETs
2.1 Introduction
As strained-silicon and USJ (Ultra Shallow Junction) techniques are widely used to optimize the carrier velocity and parasitic resistances in the MOSFET, an accurate determination of the parasitic source/drain series resistance (Rsd) for these nano-scale MOSFETs becomes a crucial issue. Since the series resistance may counteract the mobility enhancement in these strained devices, an accurate Rsd value has to be used in the extraction of intrinsic effective mobility (eff) during process development.
Furthermore, the Rsd parameter is critical to evaluate the performance of USJ engineering works.
Among several studies regarding the Rsd extraction in the past [1]-[4], Kim et al. [1]
proposed an integrated methodology to separate Rsd components and utilized the conventional Channel-Resistance method in the determination of Rsd. Although the Channel-Resistance method has been widely used [1]-[2], it is no longer suitable to nano-scale strained-silicon MOSFETs with halo implants because the laterally non-uniform channel doping as well as the uniaxial stress may result in a total resistance
devices [6]. Therefore, an adequate method that may accurately determine Rsd for nano-scale strained-silicon MOSFETs with halo implants is sorely needed.
In this work, we tackle this problem by a BSIM-based method [7]. Using this method, Rsd can be well extracted in nano-scale strained devices. The extracted Rsd will be used in the following chapters for the extraction of carrier mobility.
2.2 Devices and Experimental Setup
The devices used in this experiment were fabricated by state-of-the art IC manufacturing technology [10], which provides transistors with gate lengths ranging from 4m down to 41nm with same channel width (W = 1m) on 300mm bulk substrate. A 1.2nm nitrided gate oxide was used as a gate dielectric. Processes with ultra low HDE (Highly Doped Extension) energy and unique Spike Rapid Thermal Annealing condition were used to maintain good SCE (Short Channel Effect) control and high activation rate simultaneously. In this study, devices with different extension dosage and various stressors (Tensile/Compressive/Neutral) in NMOS were adopted to verify this extraction methodology. The testkeys constituted by the transistor arrays and calibration patterns are designed for CV measurement. Transistor arrays with Source/Drain tied together can provide enough area to characterize the capacitance in nano-scale devices. Moreover, we have used a high frequency probing system to improve the accuracy and stability of CV characterization results.
2.3 Methodology and Discussion
Fig. 2.1 shows the main procedure of our proposed BSIM-based Rsd and eff
the channel. This effect is so called bulk charge effect. Abulk is very close to 1 if the channel length is short. Since the effective channel length (Leff) plays a crucial role in the extraction of Rsd, it needs to be adequately determined first. Leff can be calculated by (LTEM - 2Lov) as depicted in Fig. 2.2 LTEM may be obtained from the in-line SEM (Scanning Electron Microscopy) measurement (with accuracy within ± 2nm) at poly patterned stage and the etching-induced length bias(L). Lov represents the overlap distance between source/drain and gate and can be extracted from CV (Capacitance-Voltage) measurement [11,12]. Fig. 2.3 shows the CV curves of different LTEM in NMOS. Cgc and Cov can be extracted at gate bias equal to 1.0V and –0.5V respectively [11]. The gate length dependency of extracted Cgc and Cov is shown in Fig.
2.4. Lov can be easily obtained from the intercept of Cgc and Cov [11,12].
Since the conventional Rsd extraction methods, which do not consider the gate length dependency of eff, need to conduct the Rsd extraction using devices with gate length ranging from short to long channel, their extraction errors are significant.
Therefore, in this work, we carried out the Rsd extraction based on the nano-scale devices with LTEM from 50nm to 83nm.
For these short-channel devices, the impact of Rsd on the drain current (Id) in the linear region (Vd = 20mV) can be modeled by Eq. (1):
assumption that the carrier velocity saturation and the bulk-charge effect are negligible.
The effective mobility (eff) in Eq. (1) can be modeled by [7]
(2)
where 0, E0 and are model fitting parameters. Eeff represents the average electric field experienced by the carriers in the inversion layer and is given by (Vg + Vth) / 6Tox for an NMOS transistor with n-type poly-silicon gate.
Since the accuracy of Eq. (1) in fitting the experimental data strongly depends on Rsd, we propose to determine Rsd by the following objective function:
(3)
where Idsi and Idmodel represent the measured drain current and the calculated Id by Eq.
(1), respectively. 0‟, E0‟ and υ‟ are the optimized model parameters that may result in a minimum model-hardware discrepancy (δmin) for a given Rsd‟
. The correlation of δ
min and Rsd‟
shown in Fig. 2.5 indicates thatδmin is sensitive to the change in Rsd‟
and we
Note that if the Rsd value is not accurate, the drain current ratio of devices with different LTEM will not be correct, as shown in Fig. 2.6. Fig. 2.7 provides the Rsd sensitivity with variations on different key parameters, where Rsd is the most sensitive to Leff but this can be overcome by careful in-line measurement. It is worth noting that the variation in
eff has to be limited to within ± 5% if ± 4% Rsd variation is the maximum tolerance level. In this work, we carried out the Rsd extraction based on the devices with LTEM
from 50nm to 83nm, where the variation of eff is within ± 5%.
To test our Rsd extraction methodology, NMOS and PMOS transistors with various extension conditions have been used. Fig. 2.8 shows the relationship between Rsd and the measured overlap capacitance (Cov) for these devices. It can be seen that when we increase the extension dose and hence the overlap distance (Lov), the extracted Rsd
indeed decreases as Cov increases. Rsd values of PMOS are around two times of NMOS.
We assume Rsd is independent of LTEM due to the following observations: (i) In Fig.
2.8, Rsd is very sensitive to overlap capacitance (Cov). However, Fig. 2.4 shows that Cov
is independent of LTEM. (ii) Based on our Tsuprem4 simulation results incorporated with halo implants, the Lov (Extension overlap distance under the poly) is independent on LTEM, as shown in Fig. 2.9.
Once Rsd is accurately determined, the intrinsic eff may be obtained using Eq. (1).
Fig. 2.10 shows the gate-length dependency of mobility (
Several explanations regarding the mobility degradation behavior in the short channel regime were proposed in the past, including halo implants and quasi-ballistic transport characteristics performed in these nano-scale devices [2,14,15]. This issue, nevertheless, deserves further study in the future. Using the extracted eff (LTEM) in Eq. (1), good agreement with the silicon data over a wide range of LTEM (41nm to 4m) can be seen, as shown in Fig. 2.11.
Please note eff extracted here is based on the charge density (Qinv) approximated by Cox×(Vg-Vth). However, some channel charge still exists in the sub-threshold region.
The better approach to obtain the Qinv result is a direct measurement of Qinv (split-CV method) from capacitance measurement, with the mobile channel charge density determined from the gate-to-channel capacitance (Cgc), as shown in Eq. (4):
gs V
V gc
inv
C dV
Q
gs
fb
(4)We will leave it for the detail discussions in chapter 3.
2.4 Verification by TCAD Simulation
To verify the proposed BSIM Rsd extraction method, we extract Rsd from simulated Id-Vg curves by Medici simulator [16] and compare with Rsd obtained from the ohmic drop in the source region of the simulated device structures. The drain bias condition is set to 50mV. Three values of specific resistivity (7x10-8, 1x10-7 and 1.3x10-7*cm2) are input to modify Rsd values and then the related Id-Vg characteristics are generated for BSIM fitting method.
extracted directly. Rsd here is defined as Rsd (c)- Rsd (c=1x10-7*cm2). As shown in Fig. 2.12, Rsd extracted from potential contour with different specific resistivity values shows the consistent trend with Rsd extracted by BSIM fitting method. It indicates that the proposed BSIM method can accurately quantify the difference of Rsd and be a suitable monitor tool for USJ (Ultra Shallow Junction) and strained process development.
2.5 Conclusion
We have proposed a BSIM-based method for Rsd and eff extraction which applies to nano-scale strained-silicon MOSFETs with halo implants. This Rsd extraction method may serve as a suitable process monitor tool for USJ (Ultra Shallow Junction) and strained process development. This method is more accurate than the conventional Channel-Resistance and Shift & Ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally non-uniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. Significant mobility degradation in short channel regime has been observed for various uniaxial stressors. The accuracy of BSIM Rsd extraction method is also verified by simulated IV characteristics with different external resistant values in short channel region. Therefore, this method may serve as a suitable process monitor tool for
References
[1] S.D. Kim, S. Narasimha, K. Rim, “An Integrated Methodology for Accurate Extraction of S/D Series Resistance Components in Nanoscale MOSFETs,” IEDM Tech.
Dig., pp. 149-152, December, 2005.
[2] K. Romanjek, F. Andrieu, T. Ernst, G. Ghibaudo, “Characterization of the effective mobility by split C(V) technique in sub 0.1 m Si and SiGe PMOSFETs,” Solid-State Electronics, vol. 49(5), pp. 721-726, May 2005.
[3] Yuan Taur, “MOSFET Channel Length: Extraction and Interpretation,” IEEE Transactions Electron Devices, vol. 47(1), pp. 160-170, January 2010.
[4] Abhisek Dixit, Anil Kottantharayil, Nadine Collaert, Mike Goodwin, Malgorzata Jurczak, Kristin De Meyer, “Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs,” IEEE Transactions Electron Devices, vol. 52(6), pp. 1132-1140, June 2005.
[5] D. Esseni, H. Iwai, M. Saito, and B. Ricco, “Nonscaling of MOSFET‟s Linear Resistance in the Deep Submicrometer Regime,” IEEE Electron Device Letter, vol.
19(4), pp. 131-133, April 1998.
[6] Hans van Meer, Kirklen Henson, Jeong-Ho Lyu, Maarten Rosmeulen, Stefan Kubicek, Nadine Collaert, and Kristin De Meyer, "Limitations of Shift-and Ratio Based Leff Extraction Techniques for MOS Transistors with Halo or Pocket Implants,” IEEE Electron Device Letters, vol. 21(3), pp. 133-136, March 2000.
[7] Y. Cheng and C. Hu, “MOSFET Modeling & BSIM3 User‟s Guide,” KAP (1999) [8] William P.N. Chen, Pin Su, K. Goto, C. Diaz, “Series Resistance and Mobility
Nano-Scale MOSFETs”, VLSI-TSA-Tech, pp.143-144, April 2006.
[10] Samuel K. H. Fung et al., “65nm CMOS High Speed, General Purpose and Low Power Transistor Technology for High Volume Foundry Application,” Symp. VLSI Tech., pp. 92-93, June 2004.
[11] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, “Improved Split C-V Method for Effective Mobility Extraction in sub-0.1-m Si MOSFETs,” IEEE Electron Device Letters, vol. 25(8), pp. 583-585, August 2004.
[12] Dieter K. Schroder, “ Semiconductor Material and Device Characterization,” 3rd edition, A John Wiley & Sons, INC., Publication (2006).
[13] http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm, ITRS 2006 Update, Process Integration, Devices, and Structures, p.9 (2006)
[14] Chu Hao, B. Cabon-Till, S. Cristoloveanu, G. Ghibaudo, “Experimental Determination of Short-Channel MOSFET Parameters,” Solid-State Electronics, vol.
28(10), pp. 1025-1030, October 1985.
[15] Antoine Cros, Krunoslav Romanjek, Dominique Fleury, Samuel Harrison, Robin Cerutti, Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Romain Wacquez, Blandine Duriez, Romain Gwoziecki, Frederic Boeuf, Hugues Brut, Gerard Ghibaudo, Thomas Skotnicki, “Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling,” IEDM Tech. Dig., pp. 1-4, December 2006.
[16] SYNOPSYS Medici User„s Manual, CA, 2004.
Characterization (Linear I
DV
G, t
ox, V
th)
Input Initial R
sdOptimized R
sd&
eff(
0,E
0,)? [Fig.5]
L
Gdependency of intrinsic
eff(
0,E
0,) obtained [Fig.10]
Optimized R
sd&
eff(
0,E
0,)? [Fig.5]
L
Gdependency of intrinsic
eff(
0,E
0,) obtained [Fig.10]
Adjust R
sdL
EFFExtraction
Parameter Table Symbol Definition ID Drain current in linear region
Cgc Gate oxide capacitance
Lov Gate-extension overlap distance; extracted from Cgc and Cov
LTEM Obtained from LSEM- L. LSEM is from in-line measurement.
L is a constant offset between LTEM and LSEM Leff LTEM-2*Lov
eff Effective mobility; Need to calibrate with Rsd by iterations Vth Threshold voltage from measurement
Abulk Bulk charge parameter; Abulk~1 in short channel region
Esat Saturation electrical field; Set Esat~
so that Vds/Esat*Leff<<10
E0
Rsd Source/Drain series resistance Input Parameter
Mobility fitting parameter Fitting Parameter
Table 2.1. Definition table of key parameters.
L TEM = L SEM -L
L EFF L ov
Gate
L ov L TEM = L SEM -L
L EFF L ov
L ov
Gate
L ov L ov
Figure 2.2. Schematic profile of MOSFET. Leff can be obtained by (LTEM – 2*Lov).
-1.0 -0.5 0.0 0.5 1.0
extracted at VG equal to 1.0V and -0.5V respectively.0 20 40 60 80 100 0
1 2 3 4 5
L
eff2*L
ovC
ov
C
gcC
gc& C
ov( a. u .)
L
TEM(nm)
Figure 2.4. Plot of Cgc & Cov versus various LTEM. Lov and Leff can be obtained
Figure 2.4. Plot of Cgc & Cov versus various LTEM. Lov and Leff can be obtained