Chapter 1 Introduction
1.3 Organization
The organization of this thesis is overviewed as follows. Chapter 2 describes the design flow for RF circuit design and proposes a unified behavior model. It also demonstrates a design example of UWB LNA. Chapter 3 reveals some examples of UWB LNA in recent researches, and chooses the capacitive cross-coupling (CCC) input matching technique for the UWB LNA design. A wideband LNA with CCC technique is designed by using the proposed behavior model in Chapter 4. The wideband LNA is also used in receiver front-end for ultra-wideband application. Chapter 5 concludes with a summary of contributions and suggestions for future work.
Chapter 2
A Unified Behavior Model Design
In order to improve the efficiency of circuit design, a design flow is presented in this chapter. In order to design the circuit by the proposed design flow, a unified RF behavior model combining the RF effects of input/output impedance, noise, nonlinearity and frequency response simultaneously is proposed. Section 2.1 addresses the design motivation of the design flow and the behavior model. The proposed behavior model consisting of input/output impedance and Gm suitable for the proposed design flow is presented in section 2.2. A Verilog-A behavior model for an ultra-wideband CMOS low noise amplifier is developed for fast and accurate system simulation in section 2.3. The analog performances of transistor level and behavior model are compared in section 2.4. The system co-simulation environment and results are presented in section 2.5.
2.1 Design Motivation
The design efficiency can be improved by the proposed circuit design flow and decreasing
the system simulation time. In order to reduce the time of system verification, behavior models are used in system co-simulation. In this thesis, a proposed behavior model can be used not only in the proposed circuit design flow to assist with the RF circuit design but also reduces the time of system verification.
In order to design a RF circuit efficiently, a valid design flow is required. Figure 5 shows the proposed design flow. To deign a circuit block of a system, it always needs to get the system specification first. The specification can tell us useful information about the system, and we can determine the system architecture by the information from specifications. The specifications of each building block can be calculated, once the system specifications and architecture are determined.
In the traditional design flow, the circuit design starts with the defined specification of each building block for system co-simulation. The design can be treated as an IP (Intellectual Property) if the design can be used in the system.
Actually, the RF circuitry usually consists of several circuit modules. Each circuit module has its assignments to assist the circuit design can meet the specifications. In the proposed design flow, the RF modules can be divided into three parts: input interface, output interface and Gm stage. The proposed design flow determines the specifications of each part. Than, we develop the behavior models of each part, a system simulation will be accomplished by these
circuit topology by using the behavior model which has been selected. In an amplifier, the input interface acts like the input matching circuit. The output interface likes the output matching and the load of the amplifier. The Gm stage is the core of the amplifier, such as common source amplifier, common gate amplifier….etc. We can build up a database of all reference designs.
If the database is large enough, the proposed behavior can assist in designing a new circuit.
The suitable topologies of a new target circuit which has difference specifications can be searched in the enormous database. After choosing the circuit topology by the database and optimize the circuit, if the specification can’t meet the system requirement, we can replace the part which has poor performance in the circuit from the database. This method is more suitable to IP application. Each part of a building block treats as an IP, and the circuit design becomes more flexible.
Analog circuit design for communication system requires different levels of parameter abstraction. There are two ways to implement design flow. A top-down design starts with behavior models using the design flow to determine the most important characteristics and gradually modify each subsystem to increase the accuracy. A bottom-up design starts with a detailed specification and determines a behavior model which can be used in system co-simulation.
Figure 5 The proposed design flow
In this chapter, we focus on the development of a behavior model and system verification of an existing design, therefore we pays attention to the bottom-up design flow. The entire transceiver is verified with BER (bit-error rate) or EVM (error vector magnitude) simulation.
Simulation with full-chip RF transceiver in transistor-level SPICE netlists is time consuming and very inefficient. Performing system simulation with analog/RF circuit elements prior to
chip implementation is crucial and urgent for designers in designing complicated wireless systems nowadays and facing very tight time-to-market schedule. In order to reduce the simulation time, behavior models for analog/RF circuits with accurate prediction are required in system simulation.
Typical characteristics must be considered and accurately modeled in RF designs including linearity, noise, gain, and frequency response. Traditionally, these characteristics are simulated with empirical models based on measurement. For example, n-port network parameter data in Touchstone format are used to characterize frequency response and noise performance. For nonlinear effect, either Taylor series or Volterra series are used instead to describe low-frequency or high-frequency distortion. The noise/frequency response and nonlinearity distortion are modeled separately without considering the impact of each other.
Several kinds of behavior model are used in the different simulation environment. In this thesis, we propose a unified RF behavior model which combines the effects of input/output impedance, noise, nonlinearity and frequency response simultaneously and reduces the overall simulation time efficiently.
2.2 The Unified Behavior Model
Here, we focus on the RF building blocks of two-port network, such as amplifiers and
filters. Mixers and switches are beyond the scope of this behavior model. As shown in Figure 6, the proposed behavior model consists of three modules: input interface module (HIF,i) for the input impedance network, core module (HGm) for the gain stage, and output interface module (HIF,o) for the output load impedance. The architecture is appropriate to the design flow which described in previous chapter. In a LTI system, the transfer function of the two port network is represented by HIF,i · HGm · HIF,o in the system simulation platform. Detailed modeling approach for each module is described in the following section.
Figure 6 UWB system simulation block diagram.
2.2.1 Modeling of Input and Output Interfaces
The input/output impedance networks of a two-port circuit shape its frequency response
and bandwidth. Though Laplace transfer function can be used to model the frequency response [4], it only defines the voltage/current transfer relation and requires additional impedance networks for the loading effect. The additional impedance networks nevertheless also shape the overall frequency response and introduce iterations in modeling. Instead of using Laplace transfer function, the proposed model employs equivalent impedance networks to portray the frequency response and the impedance matching properties of input/output interfaces at the same time. An equivalent circuit consisting of resistors, inductors, and capacitors is established to model the input matching network and the input impedance of the active device. The capacitors and inductors are used to define the reactance of HIF,i, while the resistors to define the loss including the resistor loss as well as the inductor loss and the capacitor loss. Physically, regular resistors contribute not only loss but also thermal noise.
However, the equivalent resistors in HIF,i are not the actual thermal noise sources, and are intended to model the loss only. Similarly, the load impedance and the output impedance of the active device are modeled as a network of noiseless resistors, inductors, and capacitors.
2.2.2 Modeling of Gain Stage
The gain stage can be simply modeled by a controlled signal source, depending on the input and output signal types of the active circuit topology. For example, it can be a
voltage-controlled current source (VCCS) for a common source amplifier or a current-controlled current source (CCCS) for a common-emitter amplifier. Since the input impedance of the controlled signal sources have been considered in the input interface module, HIF,i, and the output impedance of the controlled signal source can also be absorbed into the output load module, HIF,o, the controlled signal source in HGm is ideal and defines the input and output voltage/current relation either linear or nonlinear.
2.2.3 Modeling of Noise
The noise effects are lumped into an equivalent noise source instead of a noisy resistor as [4]. Hence the RF effects are modeled incrementally with iteration reduced. The noise effects of a two-port network are modeled by three equivalent noise sources in,IF,i, in,Gm and in,IF,o for the input interface, core and output interface modules, respectively. For easy extraction of noise and model consistency, in,IF,i, in,Gm and in,IF,o are all placed at the output node of each module. The explicit input noise source of the active device, for example, is absorbed to in,IF,i
in the preceding module.
2.2.4 A Simple Example of the proposed Behavior Model
Figure 7 A simple model of common-source amplifier
Figure 7 shows a simple model example of common-source amplifier. The Gm stage of this model which can determine the gain and the nonlinearity is the type of VCCS due to the common-source topology. Input interface is defined by a resistor and a capacitor, and the output interface is defined by a resonance tank for RF application. The noise sources in1 and in2 are placed at the output of the input/output interface to model the noise performance of the circuit.
2.2.5 Modeling Flow
A modeling flow is developed for the proposed unified RF behavior model as depicted in Figure 8. The two-port circuit is mapped into three behavior modules as mentioned above with RF characteristics relation equations in each module derived. This is a process of
abstracting the physical circuit topology into a simplified equivalent circuit and grouping the equivalent circuit elements into each module accordingly, which has a great influence on the iterations in later optimization processes. From the results of the transistor level simulation or measurement, the initial values for the model parameters in HIF,i, HGm and HIF,o are extracted.
The parameter extraction is followed by four optimization processes to fit the model parameters for RF characteristics of input and output impedance, frequency response, noise and nonlinear effects in sequence. The optimization is a complex task due to the correlation among the RF characteristics, and therefore proceeded incrementally by considering the noise and nonlinear effects. That is, for small input signal condition, the two-port circuit is regarded as a noiseless linear circuit in the first two optimization procedures and then a noisy linear circuit in the noise optimization. On the other hand, the circuit is considered as a noisy weak nonlinear network in the final optimization procedure. For reverse isolation concern, more iterations are required in the non-unilateral cases. The optimal model parameters are obtained if the root mean square error (RMSE) is smaller than a threshold value. Ultimately, a system simulation is performed to verify the accuracy and feasibility of the RF behavior model.
Figure 8 Unified behavioral modeling flow.
2.3 Design Example of UWB LNA
In this section, a behavior modeling example of a wideband CMOS low noise amplifier for ultra wideband applications is presented according to the above modeling procedure.
The targeting UWB LNA was fabricated in 0.18-µm CMOS technology and the circuit schematic is illustrated in Figure 9. The LNA employs stagger tuning technique, which consists of two stacked common-source stages with different resonance frequencies [5]. The output buffer in Figure 9 is for measurement purpose only and omitted in the behavior model.
The behavior model of the UWB LNA contains three interface modules, HIF,i, HIF,c and HIF,o, and two Gm-core modules, HGm,1 and HGm,2, mapping the two amplification stages as shown in Figure 10.
2.3.1 I/O Interface
A simple RLC parallel network can be used to model the interface modules for narrow band circuits. To model the input band-pass matching network and the input impedance of transistor M1 of the UWB LNA, ideal lump elements L1,L2,L3,C1,C2,C3 and R1 are used in HIF,i. HIF,c and HIF,o add RC4, RL4, RC5, and RL5 in the RLC parallel network due to the low-Q loads of the wide-band amplifier. It should be noted again that all resistors framed in Figure 10 are noiseless.
2.3.2 G
mCore
topology. The partition of the RF behavior model is determined by the critical impedance components which contribute the poles or zeros in the frequency response of the RF circuits.
Two Gm cores Gm,1 and Gm,2, as a consequence, exist in the behavior model and their initial values are extracted from the small-signal transconductance values of transistors M1 and M2. Combining HGm,1 and HGm,2 with HIF,i, HIF,c, and HIF,o, the frequency response is optimized to portray the noiseless linear characteristic of the UWB LNA.
Figure 9 Target UWB LNA circuit.
Figure 10 The UWB LNA Model.
2.3.3 Noise Sources
The noise sources considered in the RF behavior model are only thermal noise contributed by the resistors and transistors of the RF amplifier while the flicker noise of MOSFET devices is not critical. The thermal noise of a MOSFET device includes gate noise and drain current noise [6]. For calculation simplicity, the drain current noise source stays in the module of Gm-core and the gate noise source is, on the contrary, placed in the preceding interface module. The noise of HIF,c and HIF,o is also merged into the preceding Gm-core modules.
Consequently, three noise sources In1, In2 and In3 are adopted to describe the noise performance.
2.3.4 Nonlinearity
The UWB LNA is assumed weakly nonlinear and then modeled with Taylor series
2 3
1 2 3
( ) ( ) ( ) ( )
y t = α x t + α x t + α x t + ⋅⋅⋅⋅⋅
(3-1) In addition, the nonlinear effect is dominated in the second stage of the UWB LNA.Therefore, the nonlinearity is simply related to the third order coefficient (α3) of Taylor series
in HGm,2 and its initial value is set to be the performance of system simulation, the input/output impedance characteristics of behavior model must be close to transistor level circuit in the pass band of the target amplifier which operates from 2.7 to 8.5 GHz. From Figure 11 and 12, we can observe that the input/output impedance between behavior model and transistor level circuit are consistency in the pass band for both real part and image part. In the pass band, the RMSE (root mean square error) are less than 1.75 Ohm and 1.59 Ohm for real part and image part of input impedance, and 0.86 Ohm and 0.82 Ohm for real part and image part of output impedance.
Figure 11 Comparison of input impedance.
Figure 12 Comparison of output impedance.
Figure 13 Comparison of voltage gain and NF.
The comparison of voltage gain and NF are shown in Figure 13. The RMSE in pass band is less than 0.12 dB and 0.17 dB for NF and voltage gain, respectively.
The nonlinearity simulation of the UWB LNA is performed by a two-tone test with a 4.125 MHz spacing. The α3 was selected to be -1.8, so the input IP3 and P1dB agree with the transistor level simulation. The α3 is optimized in the second amplification stage, and the nonlinearity performance versus frequency has the same trend with the transistor level simulation. From Figure 14, we can find the RMSE variation of the input IP3 and P1dB are less than 1.05 dB and 0.91 dB.
Figure 14 Comparison of input IP3 and P1dB in the frequency band of interest.
Figure 15 Comparison of NF and gain with sweeping RF power at 5.016 GHz.
Figure 15 shows the gain and NF are consistency if the input power is less than input P1dB. It means that the behavioral model can be used before the large signal starts to degrade the performance. Since the input power of UWB LNA is always chosen to be small, the behavior model is suitable to the system simulation.
2.5 System Simulation Platform
2.5.1 RF/Baseband Co-Simulation Environment
Since the analog performance of behavior model agrees well with the transistor level, we replace the transistor level circuit with the behavior model in system co-simulation. Figure 16 shows the RF/Baseband co-simulation environment which is supported by the Multi-Band OFDM UWB design library in Agilent ADS platform. The “Baseband Amplifier” in Figure 16 is an ideal amplifier which can be used in baseband simulation environment. An analog
circuit can be used in this environment for RF/Baseband co-simulation when we enable the
“Analog Amplifier” and disable the “Baseband Amplifier”. The target UWB LNA can be
utilized in the block of “Analog Amplifier”. Figure 17 shows the circuit of “Analog Amplifier”. We can choose either behavior model or transistor level in the block of “Analog Amplifier” to compare the UWB LNA system performance with the transistor level and
behavior model. The gain of the variable gain amplifier (VGA) is regulated to normalize the input power of UWB receiver.
Figure 16 RF/Baseband co-simulation model.
Figure 17 RF and Analog receiver behavior model.
2.5.2 System Level Performance
Error vector magnitude (EVM) simulation is performed based on the platform in figure 16 with the Multi-Band OFDM UWB design library in Agilent ADS and the unified RF behavior model. Using the circuit envelope simulator, the platform allows cosimulating the baseband algorithms and RF Verilog-A models. The input signal is 480-Mbps OFDM modulated at 5.016 GHz with power level sweeping from −72.8 to −27.8 dBm. The simulation results shown in Figure 18 agree well with those of the transistor-level LNA with EVM RMS error less than 0.79% and the simulation time for all power sweeps is reduced 87%. The simulation results verifies the accuracy of the unified RF behavior model and demonstrates great efficiency. The simulation time in transistor level becomes longer for the larger input power due to the nonlinearity in transistor level circuit becomes severe, and increases the iteration of the simulator. The behavior model, on the other hand, doesn’t show the same increase of iteration.
Figure 18 Comparison of UWB system EVM simulation results.
Chapter 3
Capacitive Cross-Coupling UWB LNA
A design example of broad band LNA with input matching using band pass filter is modeled in in previous chapter. The NF of the LNA in chapter 2 increases rapidly in high frequency, therefore the topology presented in chapter 2 is not suitable for UWB application.
We propose a LNA topology which can achieve wideband matching, flat NF and gain from 3.1 to 10.6 GHz for UWB application. In this chapter, section 3.1 shows the design considerations and recent researches for wideband LNAs. The capacitive cross-coupling technique is chosen for UWB application, and we discuss this topology in section 3.2. Section 3.3 discusses the UWB LNA with CCC technique in the first gain stage. Section 3.4 shows the second gain stage of the UWB LNA. Section 3.5 discusses the performance of the overall UWB LNA with CCC technique. Section 3.6 summarizes this UWB LNA design.
3.1 Design Consideration of Wideband LNA
The LNA is the first module in the receiver path, which affects the performance of signal
bandwidth and noise figure of the system directly. There are several kinds of wideband LNA design topologies proposed in these years [5], [8]-[11], [14]. A wideband LNA can be
bandwidth and noise figure of the system directly. There are several kinds of wideband LNA design topologies proposed in these years [5], [8]-[11], [14]. A wideband LNA can be