Chapter 2 A Unified Behavior Model Design
2.5 System Simulation Platform
2.5.2 System Level Performance
Error vector magnitude (EVM) simulation is performed based on the platform in figure 16 with the Multi-Band OFDM UWB design library in Agilent ADS and the unified RF behavior model. Using the circuit envelope simulator, the platform allows cosimulating the baseband algorithms and RF Verilog-A models. The input signal is 480-Mbps OFDM modulated at 5.016 GHz with power level sweeping from −72.8 to −27.8 dBm. The simulation results shown in Figure 18 agree well with those of the transistor-level LNA with EVM RMS error less than 0.79% and the simulation time for all power sweeps is reduced 87%. The simulation results verifies the accuracy of the unified RF behavior model and demonstrates great efficiency. The simulation time in transistor level becomes longer for the larger input power due to the nonlinearity in transistor level circuit becomes severe, and increases the iteration of the simulator. The behavior model, on the other hand, doesn’t show the same increase of iteration.
Figure 18 Comparison of UWB system EVM simulation results.
Chapter 3
Capacitive Cross-Coupling UWB LNA
A design example of broad band LNA with input matching using band pass filter is modeled in in previous chapter. The NF of the LNA in chapter 2 increases rapidly in high frequency, therefore the topology presented in chapter 2 is not suitable for UWB application.
We propose a LNA topology which can achieve wideband matching, flat NF and gain from 3.1 to 10.6 GHz for UWB application. In this chapter, section 3.1 shows the design considerations and recent researches for wideband LNAs. The capacitive cross-coupling technique is chosen for UWB application, and we discuss this topology in section 3.2. Section 3.3 discusses the UWB LNA with CCC technique in the first gain stage. Section 3.4 shows the second gain stage of the UWB LNA. Section 3.5 discusses the performance of the overall UWB LNA with CCC technique. Section 3.6 summarizes this UWB LNA design.
3.1 Design Consideration of Wideband LNA
The LNA is the first module in the receiver path, which affects the performance of signal
bandwidth and noise figure of the system directly. There are several kinds of wideband LNA design topologies proposed in these years [5], [8]-[11], [14]. A wideband LNA can be partitioned to three parts by our behavior modeling method. The optimal design topologies of the three parts can be chosen by using the proposed behavior modeling method.
3.1.1 Basic Concerns
In designing a LNA, noise optimization and input impedance matching are usually more explored. In LNA circuits, noise sources close to the input have more contribution since they are amplified by the circuits and then appear at the output. That is the reason why the input network and the input devices are the main targets in noise reduction. Resistors are not good for input matching in LNA designs because they produce lots of thermal noise. While on-chip spiral inductors are widely used for impedance matching, they do generate thermal noise due to low quality factor; i.e. noticeable parasitic resistance. However, it is hard to accomplish the noise matching and input matching simultaneously especially, especially for a broadband LNA.
Inductive source degeneration is widely employed for input match in the narrow-band design [7]. It provides a real term ωT
L for the input impedance while generating little noise
and consuming tiny voltage headroom, and the real term is independent of frequency. It isalso found in the broadband design when the input impedance is concluded in a band-pass filter [5], [8]-[9].
Common gate topology can easily achieve broadband matching. The input impedance will be 1/gm and equal to source resistor [7]. The input impedance is in series with source resistor.
However, the minimum noise figure will be larger than 3 dB. It’s not suitable for UWB system.
3.1.2 Recent Research Reviews on Broadband LNA
Figure 19 Distributed amplifier
Several LNA design techniques had been reported for broadband communication applications. The well-developed distributed amplifier is known as its wide bandwidth. The wideband performance of the distributed amplifier is dependent on the same signal delay of each stage. However, as shown in Figure 19, it requires many stages to get wider bandwidth.
Each stage of the distributed amplifier needs chip inductors and consumes DC power. For
UWB application, many stages consumes large area due to the many chip inductors and much power. [10].
Broadband matching can be achieved by employing common-gate topology. The drawback of common-gate is the poor noise performance. A common-gate LNA was proposed to cancel the noise contribution from the input of common-gate stage as shown in Figure 20 [11].
Shunt-peaking and stagger tuning techniques are used to have flat gain form 3.1~10.6 GHz.
The noise canceling bandwidth is, however, limited when the load impedance is relative to frequency.
Figure 20 A broadband noise-canceling CMOS LNA
A capacitive cross-coupling technique was proposed to have the noise contribution form input MOSFETs [12]-[13], as shown in Figure 21. Since loads of the differential pair is
equivalent, the noise cancellation ability won’t reduce even though the operation frequency is different. In this topology, if the noise parameter of the transistor, γ, is equal to 1, the minimum noise figure is larger than 1.76 dB, and it is not good enough for some systems.
+ Vout
-+ Vin -VDD
ZL ZL
Figure 21 Capacitive cross-coupling LNA
The LNA employing stagger tuning technique consists of two common-source stages with different resonant frequencies to extend the bandwidth. A current reuse topology is used in this LNA to reduce the DC power consumption. The inductive source degeneration is used together with a three-section band-pass Chebychev filter to provide broadband input match [5], as shown in Figure 22. The noise optimization used in narrow-band design is employed and in-band average noise figure is optimized. The design begins with narrow-band-like topology and results in good broadband performance. However, there are many inductors in
input matching circuit, and the chip area becomes large.
Figure 22 A wideband LNA with band-pass filter for input matching
Figure 23 Resistive-Feedback CMOS LNA
gain and low noise figure [14], as shown in Figure 23. The chip area of this circuit is respectably small owing to no passive inductors in the circuit. The transistor M3 is an active inductor, and the capacitor CPFB compensates for parasitic capacitance CL and increase bandwidth. The resistive feedback can not only provide for matching but also flat gain, but the bandwidth of resistive feedback is hard to achieve 3.1 GHz to 10.6 GHz for specification of UWB system.
3.1.3 Summary of Wideband LNAs
Several LNA design techniques had been reported for broadband communication applications. Several methods to obtain wideband impedance matching, noise matching and flat frequency response described above. We summarize the techniques for wideband operation in Table 3 and wideband matching in Table 4. We can have a flat frequency response by combining more than one method in Table 3, but the matching method in a circuit must be only one. To choose a suitable topology for matching circuit can dominate the performance of the LNA.
Table 3. Flat frequency response methods.
Techniques of Flat Frequency Response Drawbacks
Shunt-Peaking Consumes DC power in resistor
Feedback Consumes large DC power
Stagger Tuning Use more than one inductors
Distributed Amplifier Large area and DC power
Table 4. Broadband matching methods.
Cross-Coupling Good Bad Good Moderate Small
Common Gate
Especially, this topology has a flat NF from 3.1 to 10.6 GHz. It is, therefore suitable for UWB
applications. Once the input matching topology is determined, the circuit can use the shunt-peaking and stagger tuning techniques to achieve a flat gain from 3.1 to 10.6 GHz.
3.2 Capacitive Cross-Coupling Amplifier
In these years, common source and common gate gain stages are widely used in LNA design. In common-source gain stage, a source degenerate inductor can offer the resistive impedance, and the series gate inductor can cancel the capacitive impedance to achieve narrow band input matching [7]. For wideband input matching, the reactive part of input impedance must be cancelled within a wide frequency range. We can use the band pass filter, such as LC-Ladder filter which we present last section to cancel the reactive impedance over a wide bandwidth. The NF of common-source LNA will be better if the input quality factor, Q, is increased. The NF is constrained by the low Q on-wafer inductors.
The common-gate gain stage can not only achieve the gm stage of an amplifier but also accomplish the input matching. The main drawback of common-gate amplifiers is the relatively high noise figure. Ignore the noise sources which generate from the passive components, a common gate LNA has the minimum noise factor [7]:
1
Noise Factor = + γ
(3.1) Where γ is the coefficient of channel thermal noise. When the input impedance ofcommon-gate topology is matched to 50 Ohm, the NF is usually larger than 3dB. This topology is easy to perform wideband matching, but difficult to meet the noise requirement for UWB applications.
The capacitive cross-coupling (CCC) can be used for input matching and gain enhancement [12]-[13]. The noise factor of an amplifier is expressed as:
@ stage, the gain enhancement characteristic can reduce the NF due to the output noise which is contributed from source noise becomes larger. The detail will be discussed latter.
In this section, the input matching, gain and noise performances will be demonstrated. A differential common-gate input gain stage with CCC is shown in Figure 24. In1 and In2 are the thermal noise from M1 and M2. Assume that C1 and C2 are large enough and we can ignore its impedance, the small signal of Figure 24 can be simply presented as shown in Figure 25.
Figure 24 Gain stage of capacitive cross-coupling technique
Figure 25 Small signal model of CCC technique
Let ZL1 = ZL2 = ZL, gm1 = gm2 = gm, RS1 = RS2 = RS and In1 = In2 = In = 4 kTγgm, where the
Boltzmann constant k = 1.38×10-23 J/K, and T is the absolute temperature. We only consider gain of the CCC topology is given by (detailed analysis shows in Appendix):
1 2
The noise contribution from source noise and In at output can be expressed as (3.5) and (3.6)
(detailed analysis shows in Appendix):
The coefficient “2” in equation (3.5) and (3.6) represents the sum of the two noise sources from In and RS in Figure 25. The noise factor can be calculated by equation (3.2):
2 input MOSFETs in a common-gate topology.
The common-gate topology with noise canceling architecture can also cancel the thermal noise from the input MOSFETs [11], but the noise canceling ability will become poor due to the load impedance is varied with frequency. In CCC technique, the noise canceling mechanism is independent to frequency.
3.3 The First Gain Stage with CCC Technique
The gain stage with CCC topology can achieve wideband matching and low noise. In order to use this topology for UWB application, the gain flatness from 3.1 GHz to 10.6 GHz must
be achieved. When the CCC technique is used in the UWB LNA gain stage, the flat frequency response methods listed in Table 3 can be employed. The proposed CCC LNA uses the shunt-peaking and stagger tuning methods to achieve the flat frequency response from 3.1 GHz to 10.6 GHz.
The first gain stage is very critical for a LNA. The input matching is determined by the first gain stage, and the NF is also dominated by this stage. The CCC technique is used in the first stage owing to its excellent input matching ability and the relative low NF compared with general common-gate topologies. The CCC topology can have flat and wide frequency response if the wideband load is used. In the proposed CCC UWB LNA, we use the shunt-peaking technique to perform the wideband load, and the frequency response will be more flat than a single inductor. The ZL1 and ZL2 in Figure 24 are replaced by the shunt-peaking load, as shown in Figure 26. The RLS and LS are used as the shunt-peaking load.
CP and RP are the parasitic capacitors at drain node of the MOSFETs. The parameter RP is usually the output resistance of MOSFET, ro, which doesn’t generate any noise. Assume ZL1 = ZL2 = ZL, it means that all parameters in ZL1 and ZL2 are the same, the noise factor of the CCC topology can be written by equation (3.9). The noise factor is simplified to equation (3.10) when gm = 1/2RS. From equation (3.9) and (3.10), we can find that the NF of the CCC topology is independent to RP and CP. Only the shunt-peaking components affect the NF. The
circuit can’t be arbitrary large. The sLS is limited by the resonance frequency. The impedance of LS starts to decrease when the operation frequency is higher than the resonance frequency.
The RLS is limited by the headroom of the circuit.
( )
3.1 GHz. This inductance is feasible for chip inductors. For input matching, the best value of gm is equal to 1/2RS, where RS is 50 Ohm. So the gm must be equal to 10 mA/V. Besides the gm, the parasitic capacitance at the input node will affect the input matching, too. Especially at high frequency, the effect of the parasitic capacitance is crucial. A parasitic capacitance isconsidered at 10.6 GHz, and the comparison of the variance gm and input matching is shown in Figure 27. As shown in Figure 27, once we choose the gm value to 14 mA/V, the NF is low and S11 will less than -10 dB.
Figure 26 CCC technique with shunt-peaking load
When the gm is determined, the size of the input transistors can be determined. Since the smaller size of transistors owning smaller parasitic capacitors, we can increase the overdrive voltage to keep gm equal to the determined value. But the higher overdrive voltage will drive MOSFETs into velocity saturation region and makes its noise performance worse. A optimal
Figure 27 NF and S11 v.s. gm
3.4 The Second Gain Stage
Although the first gain stage employs the shunt-peaking technique to extend the bandwidth of the UWB LNA, the bandwidth is still hard to meet the further wideband frequency range for UWB specification. As a consequence, we use the stagger tuning technique to extend the bandwidth. The schematic of the second stage is shown in Figure 28. The load of the second stage is equal to the first stage. The CP2 and RP2 are the parasitic capacitance and resistance at the output of the second stage. The RLS21 and LS21 are the shunt-peaking load for extend the bandwidth.
Figure 28 The second stage of the UWB LNA.
The second stage has the differential pair with current source, IS2, which is performed by a NMOS transistor. There are some advantages in this topology.
First, the noise contribution from the MOSFETs in the first stage can be reduced to half if the circuit is perfect matched. If the circuit mismatch occurred in the first stage and the second stage, the gain of the UWB LNA will decrease, and the noise contribution from the MOSFETs in the first stage will be larger than
2
γ . When we cascade gain stages, the
mismatch will become more serious. The ideal current source has infinity output impedance.
When the current source is connected by the source of the differential pair, the source of the differential pair can be considered as virtual ground. The signal in each output of the second
stage has the component which is relative to Vin2+ - Vin2-. The result means that the noise contribution from the MOSFETs in the first stage is determined in the second stage. The noise contribution from the input MOSFETs is only influenced by the mismatch due to the first and the second stages. The mismatch from the latter stages, like mixer, buffer, VGA or filter won’t affect the noise canceling advantage by CCC technique.
Second, the current source can bias the differential pair. Without the use of current source, there are two methods to bias the differential pair. One is to use the DC block to isolate the first and the second stage, and to bias the differential pair directly. The DC block must be implemented by the on-chip MIM capacitors. It must have some loss when the non-ideal capacitor is used to the DC block, the impedance of the non-ideal capacitor is not zero. In order to minimize the impedance of the MIM capacitor, the capacitor must be big enough. A problem occurs when the DC block is chosen as a large MIM capacitor, the parasitic capacitance becomes larger. The gain will be reduced at high frequency when the parasitic capacitance increased. There is another method to bias the differential pair. We can use the output voltage of the first stage to bias the differential pair. The drawback of this method is that the gate voltage of a MOS transistor is very sensitivity. Since the shunt-peaking technique is used in the load of the first stage, the problem becomes more serious. Because of the variation in the chip resistor is serious, the output voltage of the first stage has level shift when the load resistor is changed. The current of the differential pair may become much
larger or much smaller due to the variation of the resistor.
The differential pair bias by the current source can overcome above disadvantages. Since the current source fixed the DC current of the differential pair, the source voltage of the differential pair is allowed to variation in a range. The variation of the load resistor in the first stage won’t influence the bias of the differential pair. Although the output voltage of the first stage is variable, the Vgs of the differential pair is fixed due to the flexible source voltage since the DC current is fixed by the current source. The second stage is not sensitive to the output of the first stage, and the linearity of the second stage becomes better. The DC block does not be used in this bias method. The first stage and the second stage can be connected directly. For the stagger tuning technique, the linearity is determined by the latter stage. It is a good advantage since the linearity is determined by the second stage.
3.5 The Overall UWB LNA with CCC Technique
After understanding the characteristics of the first stage and the second stage, we can start to design the UWB LNA. The overall UWB LNA with CCC technique for input matching is shown in Figure 29. The bias tee is used to provide the dc current path and the ac signal path to M11 and M12.
After cascading the first stage and the second stage, the noise factor and gain can be
expressed in equation (3.11) and (3.12). The effect of C1, C2, Lin1 and Lin2 are omitted in (3.11)
Figure 29 The overall UWB LNA with CCC technique for input matching.
In equation (3.11), the parasitic capacitance won’t affect the noise contribution from the
first stage, but it will increase the noise contribution from the second stage. It is because the voltage gain is decreased in high frequency due to the effect of the parasitic capacitances. The noise contribution from the second stage will be relative large if the gain of the first stage becomes smaller, and the NF will become poor.
Equation (3.11) also tells us when sLS1 and sLS2 increased, the NF will be improved. The impedance of an ideal inductor will increase when the frequency is raised. Unfortunately, a practical inductor has resonance frequency due to the parasitic capacitor. When the operation frequency is higher than the resonance frequency of the inductor, the inductor will become to capacitive. The impedance of the inductor is no longer increased with the raised frequency.
Equation (3.11) also tells us when sLS1 and sLS2 increased, the NF will be improved. The impedance of an ideal inductor will increase when the frequency is raised. Unfortunately, a practical inductor has resonance frequency due to the parasitic capacitor. When the operation frequency is higher than the resonance frequency of the inductor, the inductor will become to capacitive. The impedance of the inductor is no longer increased with the raised frequency.