The remainder of this thesis is organized as follows. First, in Chapter 2, the basic ideas of circuit placement and clock network distribution will be introduced. The related liter-atures of low power design will also be surveyed thoroughly in Chapter 2. The activity analysis method which we utilize to obtain the precisely distribution of modules’ activity and the optimal gated clock topology will be described in Chapter 3.
In Chapter 4, the techniques constructing the LPGC Placer will be presented. In order to demonstrate our LPGC Placer, both the placement results from LPCG Placer and a general placement method without considering the gated clock topology will be fed into a real low power gated clock router [20, 23] to find out the extra power consumption saving percentage of LPGC Placer in Chapter 5. Finally, the conclusions and future work will also be given in the remaining of Chapter 5.
Chapter 2
Preliminaries and Literatures Survey
In this chapter, the basic concepts of placement and clock routing problems will be pre-sented, and the previous related researches will be reviewed.
2.1 Basic Concepts of General Placement
Placement is a crucial step in physical design cycle. A poor placement results in larger area occupation, performance degradation, higher power consumption, and even the un-evenly thermal distribution. A poor placement also leads to a difficult or impossible rout-ing task. The input of the placement phase is a set of blocks, the information of terminals of each block, and the netlist which describes the connectivity of all modules.
The placement has a deeply impact on the performance of overall layout because an ill-placed layout cannot be improved by any high quality routing algorithm. In other word, the overall quality of the layout such as area, power, total wire-length or thermal distribution is mainly determined in the placement phase. For example, Fig. 2.1 shows two different placements of a circuit, you can see that Fig. 2.1(a) is better than Fig. 2.1(b) since the total wire-length of Fig. 2.1(a) is seem to be shorter than Fig. 2.1(b)’s.
2.1.1 Problem Formulation
Given a set of circuit modules, a placement problem is to arrange modules on the layout surface to satisfy some prescribed constraints such as non-overlapping criterion or cir-cuit boundary constraint, and to optimize certain objective functions such as total area,
A
Fig. 2.1: Comparison between two placements. (a) The placement with shorter total wire-length. (b) The placement with longer total wire-wire-length.
total estimated wire-length, total power consumption or/and thermal balancing. At the placement level, a circuit is considered as a group of rectangular modules with fixed geo-metric ratios. The interconnect relationships among each modules are described in the netlist of interconnect. The different operations such as rotate, flip, move, and swap can be performed on the modules to achieve an optimal placement according to different cost functions.
The formal definition of placement problem is as follows.
Given a set of modules M = {m1, m2, · · · , mn}, a set of signals S = {s1, s2, · · · , sk}, and a set of slots/locations L = {L1, L2, · · · , Lp} where p ≥ n, Smi is a set of signals with Smi ⊆ S for each module mi, and Msi is a set of modules with Msi = {mj | si ∈ Smj; ∀mj ∈ M} for each signal si. Msi is called a signal net. The placement problem is to assign each mj ∈ M to an unique location Lj such that some objective function, f (M, S, L), is
optimized. Sometimes a subset of modules in M is pre-assigned to several specific locations.
The placement problem is extended to be the floorplanning problem if the geometries or aspect ratios of given modules are more flexible. For example, the modules can be rotated, their shapes can be modified, or the locations of pins can be changed. It is obvious that floorplanning is a generalized version of placement problem, and has higher flexibility to place the modules than the placement’s. Of course, it is more complicated.
2.1.2 Wire-length Estimation
The first objective of the high performance integrated circuits is to maximize the operat-ing frequency or to minimize the total delay of the whole system. This objective can be complete by minimizing the length of the critical nets. Usually, it could be approximated by minimization of the length of the longest signal wire-length. After this approximated approach, the objective for maximizing the operating frequency becomes a simpler prob-lem.
Although the real signal wire-lengths are not available at placement level, a placer needs to model the actual topology of the interconnection effectively and accurately. By using the interconnection graph structure, the requirements could be satisfied. The inter-connection graph structure for modeling the inter-connection between two terminals is simply an edge between the two vertices corresponding to the terminals. For the purpose of mod-eling a net with more terminals, rectilinear steiner trees are used as shown in Fig. 2.2(a) to estimate the optimal signal paths for a net. This model is seldom used by placers, because of the NP-completeness of steiner tree problem.
As a result, minimum spanning tree(shown in Fig. 2.2(b)) and semi-perimeter rep-resentations(shown in Fig. 2.2(c)) are the most two commonly used models to represent the connections of a net in the placement level. In th Minimum spanning tree model, connections are allowed to branch only at the pins. The other one is semi-perimeter rep-resentation, it can estimate the wire-length effectively by bounding pins with a rectangle
(a) (b)
(c) (d)
Fig. 2.2: Models of wire-length estimation. (a) Steiner tree. (b) Spanning tree. (c) Semi-perimeter. (d) Complete graph.
then calculates its semi-perimeter.
Complete graph interconnection is shown in Fig. 2.2(d). This method causes many redundant wires, and result in longer wire length. The purpose of such model is to give one the upper bound of a net’s wire-length.