Low Power Zero-skew Clock Routing

For a long time, the general theory behind clock design was that the signal should be kept as clean as possible, and that a circuit designer should not interrupt or disable a clock signal. Traditionally, all the clock routing algorithms aim to solve the clock skew and minimum clock wirelength. However, as the technology keep improving and keep shrinking the feature size, the interconnect power has the same magnitude as compared to gate power [2, 3, 4, 19]. Clock network is a network with long wires and highly switching

6 5

1

2

7

8 3

4

root merging segment

Fig. 2.10: A tree of merging segments. Solid lines are merging segments and dotted lines indicate edges between merging segments. The squares represent the clock sinks.

activity, hence, the higher power. It has been researched that the clock power is at least 40% of the total power for a typical microprocessor [19].

Therefore, today’s research focus on distributing a clock network with minimizing clock skew, wirelength, timing and finally clock power. It is a new field with many chances and improvements in it.

Activity Driven Clock Design

Clock power can be saved by disabling clock signals from inactive registers(flip-flops) in idle circuit portions. We can carefully insert the controlling logic gates to control the clock signals in front of registers. By shutting down idle registers, the downstream combinational circuitry and data transmission path would not be active so that saving a substantial amount of power. This technique is so-called gated clock routing or clock gating.

By performing sophisticated algorithms, one could achieved the low power clock

net-work with inserting the control gates. Since registers that should be gated or merged together may be placed far apart, it is possible that gating control wirelength will finally be increased and the total so that the clock power finally goes up.

The authors in [22, 25] suggested that by putting the pseudo net between commonly-gated registers together in the netlist and then the placer would tends to put them closely.

However, here are the drawbacks in this idea:

1. The amount of pseudo nets would be enormously so that the weight of net which made by manually dictated would probably be failed when handling larger circuits.

2. There is no way to handle the global optimization.

3. The pseudo net would destroy the timing of critical nets.

Gated clock routing for microprocessor design.

In this publication, the authors have proposed an approach for clock tree routing, that ensures zero-skew and reduces the clock power dissipation by minimizing the effective switched capacitance at the internal nodes of the tree. This algorithm refined the DME algorithm which we have known as a multi-purpose clock router. The authors [23, 20]

replace the traditional clock routing objective from minimizing total wirelength to mini-mizing total switched capacitance.

The algorithm first formulates the clock network power and clock control network power as follows: Consider a clock tree without gates, the power dissipation on a partic-ular clock edge eiis defined as

P owerei = |ei|c0f V_dd² (2.6)

where |e_i|c₀ represent the switched capacitance of this clock edge(c₀ is the unit wire capacitance and e_i is the wirelength of the clock edge e_i). The power dissipation for gated clock network, the Equation (2.6) should be modified as:

P ower_ei,gated= |e_i|c₀f V_dd²P (e_i) (2.7)

with additional consideration on the switching activity of the clock edge e_i. Since the operation frequency and supply voltage are fixed we define effective switched capacitance at any edge as:

SC_ei = (|e_i|c₀+ C_i)P (e_i) (2.8) where the C_i represents the load capacitance of the clock edge e_i. Thus, the switched capacitance of the entire gated clock network can be defined as:

SC_GCN =^X

∀ei

SC_ei (2.9)

Finally, we take the gated clock control network into account. We can follow the definition as same as Equation (2.9):

SCGCCN = 1 2

X

∀g_ei

(c0|gei| + Cg)Ptr(gei) (2.10)

where the |g_ei| and P_tr(g_ei)represent the wirelength and transition probability of the gated clock control wire g_ei. We assume that the source of the gated clock control network is be laid in the center of the chip, C_g means the control gate’s capacitance. The objective of this routing algorithm is to minimize the term SC = SC_GCN + SC_GCCN through DME algorithm.

First, given all the clock sinks’ locations, they could built a binary tree which represent the gated clock topology which could minimize SC. Then, by passing this topology to DME router hence force it to route this clock network with zero-skew. As we can realize from the idea of this algorithm, there are many aspects which we could improve.

Because they have no process for global optimization, they may achieve either a non-optimal solution or a poor solution. Our work improves these drawbacks then provides a process or a good seed for global optimization.

Chapter 3

Activity analysis and optimal gated clock topology

In this chapter, the activity analysis and optimal gated clock topology will be introduced.

As we mentioned in the previously chapters, the dynamic power of a CMOS circuitry is proportional to its switching activity. The VLSI designers can utilize different techniques on their designs to reduce the power consumption as long as the correct distribution of activity among every portion of their circuits is available. However, obtaining the precise activity distribution of each module is not an easy task. After the correct activity distribu-tion is obtained, a procedure of constructing the optimal low power gated clock topology can be executed. LPGC Placer develops a procedure to build the optimal gated clock topology. Before introducing the em LPGC placer, the essential ideas of activity analysis and the optimal gated clock topology are presented in this chapter.

3.1 Activity Analysis

Since the problem of placement which we deal with is at the physical design level, the in-formation of activity from the higher level of the design must be acquired. Many different methods have been investigated in this field [20, 22, 50, 51, 52, 53, 54, 55, 56, 57], two of them which are related to our work will be introduced.